Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

Abstract: Provided is a method for preventing or treating a liver disease, including administering a therapeutically effective amount of pharmaceutical composition to a subject in need, and the pharmaceutical composition includes the isothiocyanate structural modified compound and a pharmaceutically acceptable carrier thereof.

Abstract: An electronic device has a narrow viewing angle state and a wide viewing angle state, and includes a panel and a light source providing a light passing through the panel. In the narrow viewing angle state, the light has a first relative light intensity and a second relative light intensity. The first relative light intensity is the strongest light intensity, the second relative light intensity is 50% of the strongest light intensity, the first relative light intensity corresponds to an angle of 0°, the second relative light intensity corresponds to a half-value angle, and the half-value angle is between ?15° and 15°. In the narrow angle state, a third relative light intensity at each angle between 20° and 60° or each angle between ?20° and ?60° is lower than 20% of the strongest light intensity.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: A display device including a first light emitting unit, a second light emitting unit, a first optical layer and a second optical layer is disclosed. The first optical layer is disposed on at least one of the first light emitting unit and the second light emitting unit, and the first optical layer includes a collimating layer. The second optical layer is disposed on the first light emitting unit. The second optical layer is configured to scatter a first light emitted from the first light emitting unit but does not scatter a second light emitted from the second light emitting unit.

Abstract: A method for designing a power distribution network of a circuit system includes the following steps: determining positions of a plurality of power source nodes; estimating a current distribution condition of the circuit system; and creating a first part of the power distribution network according to at least the positions of the power source nodes.

Abstract: A method for designing a power distribution network of a circuit system includes the following steps: determining positions of a plurality of power source nodes; estimating a current distribution condition of the circuit system; and creating a first part of the power distribution network according to at least the positions of the power source nodes.

Abstract: A method for designing a power distribution network of a circuit system includes the following steps: determining positions of a plurality of power source nodes; estimating a current distribution condition of the circuit system; and creating a first part of the power distribution network according to at least the positions of the power source nodes.

Abstract: A method for designing a power distribution network of a circuit system includes the following steps: determining positions of a plurality of power source nodes; estimating a current distribution condition of the circuit system; and creating a first part of the power distribution network according to at least the positions of the power source nodes