Patents by Inventor Kuo-Tai Tseng

Kuo-Tai Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6781225
    Abstract: An integrated circuit chip with ball-grid array solder balls is packaged as a module without being sealed in protective glue. The IC chip is mounted on an insulating substrate with pads to support the solder balls. The pads are connected to a second set of pads along the periphery of the substrate. Leads are pressed against the second set of pads for external connections. A second IC chip may be pressed against the other side of the substrate to increase the external connections.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: August 24, 2004
    Assignee: ChipMOS Technologies Inc.
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng
  • Publication number: 20040150062
    Abstract: A simplified image sensor module of the invention includes a substrate, a frame layer, a photosensitive chip, wires, and a transparent layer. The substrate has an upper surface and a lower surface. The frame layer has a first surface and a second surface. The first surface is arranged on the upper surface of the substrate, and a cavity is formed between the substrate and the frame layer. The photosensitive chip has bonding pads and is mounted to the upper surface of the substrate and located within the cavity. The wires electrically connect the bonding pads of the photosensitive chip to the substrate. The transparent layer is arranged on the second surface of the frame layer and is formed with a convex portion at a position corresponding to the photosensitive chip. Accordingly, the photosensitive chip may receive focused optical signals passing through the convex portion.
    Type: Application
    Filed: February 4, 2003
    Publication date: August 5, 2004
    Inventors: Jackson Hsieh, Jichen Wu, Bruce Chen, Kuo-Tai Tseng
  • Publication number: 20040140419
    Abstract: An image sensor with improved sensor effects includes a substrate, a frame layer, a photosensitive chip, wires, and a transparent layer. The substrate has an upper surface and a lower surface. Signal input terminals are formed at a periphery of the upper surface, and projections with the same height are formed at a central portion of the upper surface. The frame layer is arranged at a periphery of the substrate to form a U-shaped structure and a cavity together with the substrate. The signal input terminals and projections are inside the cavity. The photosensitive chip is arranged on the projections. The wires electrically connect the photosensitive chip to the signal input terminals of the substrate. The transparent layer is placed on the frame layer to cover the photosensitive chip. By placing the photosensitive chip on the projections, better flatness and thus better sensor effects may be obtained.
    Type: Application
    Filed: January 16, 2003
    Publication date: July 22, 2004
    Inventors: Jackson Hsieh, Jichen Wu, Bruce Chen, Kuo-Tai Tseng
  • Patent number: 6696738
    Abstract: An image sensor includes a substrate, a frame layer, a photosensitive chip and a transparent layer. The substrate is composed of spaced metal sheets. Each metal sheet includes a first board, a second board and a third board connecting the first and second boards, which are located at different heights. The frame layer has an upper surface and a lower surface. The frame layer covers and seals the metal sheets while exposes bottom surfaces of the second boards. The frame layer is formed with a chamber. Bottom surfaces of the first boards are exposed through the chamber, and a transparent region communicating with the chamber is formed on the upper surface of the frame layer. The photosensitive chip formed with bonding pads is disposed within the chamber. The bonding pads contact the bottom surfaces of the first boards. The transparent layer is mounted on the frame layer.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: February 24, 2004
    Assignee: Kingpak Technology Inc.
    Inventors: Hsiu Wen Tu, Kuo-Tai Tseng
  • Publication number: 20030116862
    Abstract: An integrated circuit chip with ball-grid array solder balls is packaged as a module without being sealed in protective glue. The IC chip is mounted on an insulating substrate with pads to support the solder balls. The pads are conducted to a second set of pads along the periphery of the substrate. Leads are pressed against the second set of pads for external connections. A second IC chip may be pressed against the other side of the substrate to increase the external connections.
    Type: Application
    Filed: December 6, 2002
    Publication date: June 26, 2003
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng
  • Publication number: 20020050378
    Abstract: The IC chips of a multiple IC chip module are mounted in stack in a ceramic substrate, which has good heat dissipating capability. At least one IC chip is mounted on top of the ceramic substrate and at least one other IC chip is mounted at the bottom of the ceramic substrate. The bonding pads along the periphery of the ceramic substrate are lead-bonded to a second substrate with printed wiring on at least one of the surfaces and solder connection at the bottom. The IC chip is separated from the second substrate by a resin to cushion the stress due to difference in thermal expansion coefficients of the IC chip and the second substrate.
    Type: Application
    Filed: May 24, 2001
    Publication date: May 2, 2002
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng
  • Patent number: 6137174
    Abstract: A package for multiple IC chip module. The IC chip is attached to electric wires on ceramic substrate which has good heat dissipating capability. The bonding pads along the periphery of the ceramic substrate are lead-bonded to a second substrate with printed wiring on at least one side of the surfaces and ball grid array at the bottom surface. Double-sided printed wiring can be used to provide multiple-layered interconnection. The IC chip is separated from the second substrate by a resin to cushion the stress due to difference in thermal expansion coefficients of the IC chip and the second substrate.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: October 24, 2000
    Assignee: ChipMOS Technologies Inc.
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng
  • Patent number: 6034425
    Abstract: A micro ball grid array package is devised for a multiple-chip module (MCM). The IC chips in the package are butted together to save space. The bonding pads for the lower IC chip or chips are placed along the edges not butted with one another. The bonding pads of the chips are wire-bonded to a printed wiring plate, which has via holes through the printed wiring plate for connection to the ball grid array at the other side of the printed wiring plate and for surface mounting to a printed circuit board. A heat dissipating plate may be placed at the top of the IC chips away from the ball grid array.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: March 7, 2000
    Assignee: ChipMOS Technologies Inc.
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng
  • Patent number: 6023097
    Abstract: A micro ball grid array package is devised for a multiple-chip module (MCM). The IC chips in the package are stacked to save space. The bonding pads for the lower IC chip or chips are placed along the edges where the pads are not masked by the stacking of the upper chip or chips. When there are more than one chip at each level of the stacking, the IC chips at each level are butted with each other to further save space. The bonding pads of the chips are wire-bonded to a printed wiring plate, which has via holes through the printed wiring plate for connection to the ball grid array at the other side of the printed wiring plate and for surface mounting to a printed circuit board. A heat dissipating plate may be inserted at the bottom of the IC chips away from the stacking surface.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: February 8, 2000
    Assignee: ChipMOS Technologies, Inc.
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng