Patents by Inventor Kuo-Ting YANG

Kuo-Ting YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136183
    Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Yu-Shih Wang, Hong-Jie Yang, Chia-Ying Lee, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11120886
    Abstract: A gate driving circuit comprises a plurality of shift registers coupled in serial. An nth shift register includes a driving circuit, a pull-up circuit and a first auxiliary voltage regulator circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a clock signal and output a gate signal according to the clock signal. The pull-up circuit is electrically coupled to the driving circuit. The first auxiliary voltage regulator circuit is electrically coupled to the pull-up circuit and a second node. The first auxiliary voltage regulator circuit is configured to receive a control signal and the second node corresponding to a second voltage.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: September 14, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Er-Lang Deng, Yuan-Nan Chiu, Chih-Yuan Wu, Yu-Lin Huang, I-Sheng Lin, Kuo-Ting Yang
  • Publication number: 20200286572
    Abstract: A gate driving circuit comprises a plurality of shift registers coupled in serial. An nth shift register includes a driving circuit, a pull-up circuit and a first auxiliary voltage regulator circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a clock signal and output a gate signal according to the clock signal. The pull-up circuit is electrically coupled to the driving circuit. The first auxiliary voltage regulator circuit is electrically coupled to the pull-up circuit and a second node. The first auxiliary voltage regulator circuit is configured to receive a control signal and the second node corresponding to a second voltage.
    Type: Application
    Filed: November 11, 2019
    Publication date: September 10, 2020
    Inventors: Er-Lang DENG, Yuan-Nan CHIU, Chih-Yuan WU, Yu-Lin HUANG, I-Sheng LIN, Kuo-Ting YANG