Abstract: A multiplier with in-path subnormal handling includes a zero counter, a multiplication circuit, a comparator and a rounder. The zero counter receives a first mantissa and a second mantissa, and output a zero count by adding up a first trailing-zero count, a second trailing-zero count, and at least one of a first leading-zero count and a second leading-zero count. The multiplication circuit outputs a mantissa product by multiplying the first mantissa and the second mantissa. The comparator outputs a sticky bit by comparing the zero count and a sticky portion width varying according to the most significant bit of the mantissa product. The rounder outputs a mantissa result by performing a rounding operation according to the mantissa product and the sticky bit.

Abstract: A mixed-precision multiplication circuit that computes according to a second operand and a first operand is provided. The first operand includes an exponent and a mantissa, and the mixed-precision multiplication circuit includes a subset selector and a mantissa multiplier. The subset selector is configured to store the second operand and receive the exponent. The subset selector selects a subset from a plurality of subsets according to the exponent, with the plurality of subsets representing the second operand. The mantissa multiplier is coupled to the subset selector for receiving a multiplicand associated with the selected subset, and configured to receive the mantissa. The mantissa multiplier generates a product by performing a multiplication according to the multiplicand and the mantissa, and the mixed-precision multiplication circuit outputs a result according to the product.

Abstract: An adder circuitry for adding two floating-point operands is provided. The first operand includes a first exponent and a first mantissa, the second operand includes a second exponent and a second mantissa. The adder circuitry includes a least significant bit (LSB) handler, an exponent subtractor, a near-path logic circuit, a far-path logic circuit, and a selection logic circuit. The LSB handler generates an LSB result to reflect whether LSBs of the first and second exponent are identical. The exponent subtractor computing an exponent difference between the first and second exponent. The near-path logic circuit computes a near-path result according to the first and second mantissa. The far-path logic circuit computes a far-path result according to the exponent difference, the first mantissa and the second mantissa. The selection logic circuit selects one of the near-path result and the far-path result according to the exponent difference.

Abstract: In a novel computation device, a plurality of partial product generators is communicatively coupled to a binary number multiplier. The binary number is partitioned in the computation device into non-overlapping subsets of binary bits and each subset is coupled to one of the plurality of partial product generators. Each partial product generator, upon receiving a subset of binary bits representing a number, generates a multiplication product of the number and a predetermined constant. The multiplication products from all partial product generators are summed to generate the final product between the predetermined constant and the binary number. The partial product generators are constructed by logic gates and wires connected the logic gates including a AND gate. The partial product generators are free of memory elements.

Abstract: In a novel computation device, a plurality of partial product generators is communicatively coupled to a binary number multiplier. The binary number is partitioned in the computation device into non-overlapping subsets of binary bits and each subset is coupled to one of the plurality of partial product generators. Each partial product generator, upon receiving, a subset of binary bits representing a number, generates a multiplication product of the number and a predetermined constant. The multiplication products from all partial product generators are summed to generate the final, product between the predetermined constant and the binary number. The partial product generators are constructed by logic gates and wires connected the logic gates including a AND gate. The partial product generators are free of memory elements.

Abstract: In a novel computation device, a plurality of partial product generators is communicatively coupled to a random number. The random number is partitioned in the computation device into non-overlapping subsets of binary bits and each subset is coupled to one of the plurality of partial product generators. Each partial product generator, upon receiving a subset of binary bits representing a number, generates a multiplication product of the number and a predetermined constant. The multiplication products from all partial product generators are summed to generate the final product between the predetermined constant and the random number.