Abstract: A pixel circuit of a display panel includes a driving transistor, first to fifth transistors, and a light emitting device. The driving transistor includes a first terminal, a second terminal and a gate terminal. The first transistor is coupled between a power supply terminal and the first terminal of the driving transistor. The second transistor is coupled between the first terminal of the driving transistor and the gate terminal of the driving transistor. The third transistor is coupled between the second terminal of the driving transistor and the gate terminal of the driving transistor. The fourth transistor is coupled between a data input terminal and the second terminal of the driving transistor. The fifth transistor is coupled to the second terminal of the driving transistor. The light emitting device is coupled between the fifth transistor and a reference voltage terminal.

Abstract: A driving device includes a voltage regulator, a voltage generator, and a first NMOSFET. The voltage regulator is coupled between a first high-voltage terminal and the output terminal of the driving device. The voltage regulator receives the first high voltage of the first high-voltage terminal. The voltage regulator steps down the first high voltage to generate a supply voltage. The voltage generator is coupled to a second high-voltage terminal and the output terminal of the driving device. The voltage generator provides a reference voltage for the output terminal of the driving device. The reference voltage is substantially lower than the supply voltage. The first NMOSFET is coupled between the output terminal of the driving device and a low-voltage terminal.

Abstract: A driving device includes a voltage regulator, a voltage generator, and a first NMOSFET. The voltage regulator is coupled between a first high-voltage terminal and the output terminal of the driving device. The voltage regulator receives the first high voltage of the first high-voltage terminal. The voltage regulator steps down the first high voltage to generate a supply voltage. The voltage generator is coupled to a second high-voltage terminal and the output terminal of the driving device. The voltage generator provides a reference voltage for the output terminal of the driving device. The reference voltage is substantially lower than the supply voltage. The first NMOSFET is coupled between the output terminal of the driving device and a low-voltage terminal.

Abstract: An optical sensing device, including a first power rail, a second power rail, and a plurality of optical sensing elements arranged in an array, is provided. Each optical sensing element can include a photo diode, a reset switch, and a buffer. The reset switch can have a control terminal to receive a reset signal. A first terminal of the reset switch can be coupled to the first power rail and a second terminal of the reset switch is coupled to the photo diode. A first terminal of the buffer can be coupled to the second power rail, a second terminal of the buffer can be coupled to the second terminal of the reset switch and the photo diode, and a third terminal of the buffer is configured to provide a sensing signal. The second power rail is separate or independent from the first power rail.

Abstract: A readout circuit is provided. The readout circuit is coupled to a pixel circuit for reading out signals from the pixel circuit. The readout circuit includes a biasing circuit. The biasing circuit includes a cascode transistor and a biasing transistor. A first terminal of the cascode transistor is coupled to an output terminal of the biasing circuit and the pixel circuit. A second terminal of the cascode transistor is coupled to a first terminal of the biasing transistor. A second terminal of the biasing transistor is coupled to a negative voltage.

Abstract: A readout circuit is provided. The readout circuit is coupled to a pixel circuit for reading out signals from the pixel circuit. The readout circuit includes a biasing circuit. The biasing circuit includes a cascode transistor and a biasing transistor. A first terminal of the cascode transistor is coupled to an output terminal of the biasing circuit and the pixel circuit. A second terminal of the cascode transistor is coupled to a first terminal of the biasing transistor. A second terminal of the biasing transistor is coupled to a negative voltage.

Abstract: A signal processing circuit for processing a sensing signal from a sensing circuit includes a plurality of input capacitors, an amplifier, an input switch group, a plurality of storage capacitors and a plurality of storage control switches. The plurality of input capacitors are configured to receive the sensing signal from one of a differential input nodes of the signal processing circuit and couple the sensing signal to a plurality of floating nodes. The amplifier, coupled to the plurality of floating nodes, is configured to amplify the sensing signal coupled from the plurality of floating nodes. The input switch group is coupled between the plurality of floating nodes and the plurality of input capacitors. The plurality of storage control switches, coupled between the plurality of floating nodes and the plurality of storage capacitors, are configured to couple offset information of the plurality of input capacitors to the plurality of storage capacitors.

Abstract: A signal processing circuit for processing a sensing signal from a sensing circuit includes a plurality of input capacitors, an amplifier, an input switch group, a plurality of storage capacitors and a plurality of storage control switches. The plurality of input capacitors are configured to receive the sensing signal from one of a differential input nodes of the signal processing circuit and couple the sensing signal to a plurality of floating nodes. The amplifier, coupled to the plurality of floating nodes, is configured to amplify the sensing signal coupled from the plurality of floating nodes. The input switch group is coupled between the plurality of floating nodes and the plurality of input capacitors. The plurality of storage control switches, coupled between the plurality of floating nodes and the plurality of storage capacitors, are configured to couple offset information of the plurality of input capacitors to the plurality of storage capacitors.

Abstract: The present invention discloses a sheet winding structure to reduce indentation transfer occurring because of sheet thickness or adhesive colloidality of the innermost layer of the sheet. The sheet winding structure comprises: a winding core having an outer surface, wherein the outer surface of the winding core comprises a recess thereon; and a sheet winded over the outer surface of the winding core, wherein a beginning portion of the sheet is disposed in the recess.

Abstract: The present invention discloses a sheet winding structure to reduce indentation transfer occurring because of sheet thickness or adhesive colloidality of the innermost layer of the sheet. The sheet winding structure comprises: a winding core having an outer surface, wherein the outer surface of the winding core comprises a recess thereon; and a sheet winded over the outer surface of the winding core, wherein a beginning portion of the sheet is disposed in the recess.

Abstract: The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.

Abstract: The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.

Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle ? less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle ? less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle ? less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.