Abstract: An optical lens assembly includes, from an object side to an image side, at least four optical lens elements. At least one of the at least four optical lens elements includes an anti-reflective coating. The at least one optical lens element including the anti-reflective coating is made of a plastic material. The anti-reflective coating is arranged on an object-side surface or an image-side surface of the at least one optical lens element including the anti-reflective coating. The anti-reflective coating includes at least one coating layer. One of the at least one coating layer at the outer of the anti-reflective coating is made of ceramics. The anti-reflective coating includes a plurality of holes, and sizes of the plurality of holes adjacent to the outer of the anti-reflective coating are larger than sizes of the plurality of holes adjacent to the inner of the anti-reflective coating.

Abstract: An optical lens assembly includes, from an object side to an image side, at least four optical lens elements. At least one of the at least four optical lens elements includes an anti-reflective coating. The at least one optical lens element including the anti-reflective coating is made of a plastic material. The anti-reflective coating is arranged on an object-side surface or an image-side surface of the at least one optical lens element including the anti-reflective coating. The anti-reflective coating includes at least one coating layer. One of the at least one coating layer at the outer of the anti-reflective coating is made of ceramics. The anti-reflective coating includes a plurality of holes, and sizes of the plurality of holes adjacent to the outer of the anti-reflective coating are larger than sizes of the plurality of holes adjacent to the inner of the anti-reflective coating.

Abstract: The present disclosure discloses a memory signal calibration apparatus and a memory signal calibration method. A gating circuit generates a data strobe enablement setting signal according to a setting control signal, generates an enabling state of the data strobe enablement signal and performs gating on a data strobe signal according to the enabling state to generate a gated data strobe signal.

Abstract: A test method for a delay circuit and a test circuitry are provided. The test circuitry incudes the delay circuit that essentially includes multiple serially connected logic gates, a clock pulse generator at an input end of the delay circuit for generating one or more cycles of clock signals, and a counter at an output end of the delay circuit for counting the clock signals passing through the delay circuit. The test circuitry implements a test mode by switching lines to the clock pulse generator and the counter. The test circuitry relies on a comparison result of a counting result made by the counter and a number of the cycles of the clock signals to test any failure of the delay circuit.

Abstract: A reference potential generating circuit includes at least one upper-potential selection switch, at least one lower-potential selection switch, a resistor string and at least one multiplexer. Each upper-potential selection switch receives an upper-voltage signal, and one of the upper-potential selection switches is turned on. Each lower-potential selection switch receives a lower-voltage signal, and one of the lower-potential selection switches is turned on. The resistor string is coupled between the upper-potential selection switch and the lower-potential selection switch. The multiplexer includes a plurality of input ends and an output end. The input ends are coupled to ends of the resistors one to one, and the output end of one of the multiplexers outputs a reference potential signal. A control method for the aforementioned reference potential generating circuit is further provided here.

Abstract: Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.

Abstract: A phase interpolation device and a multi-phase clock generation device are provided. The phase interpolation device includes a digital controller circuit and a phase interpolator that includes a capacitor and circuit branches, which are controlled by the digital controller circuit to generate an n-th phase clock of N phase clocks between first and second input clocks. When the n-th phase clock is generated, the digital controller circuit controls, in response to appearances of rising edges of the first input clock, the circuit branches to charge the capacitor using (N?n+1)×M ones of the first current source, and controls, in response to appearances of rising edges of the second input clock, the circuit branches to use N×M ones of the first current source to charge the capacitor. N, M, n are integers.

Abstract: A phase interpolation device and a multi-phase clock generation device are provided. The phase interpolation device includes a digital controller circuit and a phase interpolator that includes a capacitor and circuit branches, which are controlled by the digital controller circuit to generate an n-th phase clock of N phase clocks between first and second input clocks. When the n-th phase clock is generated, the digital controller circuit controls, in response to appearances of rising edges of the first input clock, the circuit branches to charge the capacitor using (N?n+1)×M ones of the first current source, and controls, in response to appearances of rising edges of the second input clock, the circuit branches to use N×M ones of the first current source to charge the capacitor. N, M, n are integers.

Abstract: Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.

Abstract: A test method for a delay circuit and a test circuitry are provided. The test circuitry incudes the delay circuit that essentially includes multiple serially connected logic gates, a clock pulse generator at an input end of the delay circuit for generating one or more cycles of clock signals, and a counter at an output end of the delay circuit for counting the clock signals passing through the delay circuit. The test circuitry implements a test mode by switching lines to the clock pulse generator and the counter. The test circuitry relies on a comparison result of a counting result made by the counter and a number of the cycles of the clock signals to test any failure of the delay circuit.

Abstract: A detection circuit and a detection method are provided. The detection circuit is suitable for a system-on-chip (SoC). The SoC is coupled to an alarm pin of a DDR4 memory through a connection pad, and the detection circuit includes a control circuit coupled to the connection pad. In response to the DDR4 memory performing a refresh process or a specific event occurring, the control circuit outputs a test signal with a first voltage level to the connection pad, and determines whether a voltage level of the connection pad is tied to a second voltage level. In response to determining that the voltage level of the connection pad is tied to the second voltage level, the control circuit outputs an interrupt signal to a CPU of the SoC, and the interrupt signal indicates that the alarm pin of the DDR4 memory is not controlled normally by the DDR4 memory.

Abstract: A method of foreground auto-calibrating data reception window for a DRAM system is disclosed. The method comprises receiving data strobe and data from a DRAM of the DARM system, capturing a data strobe clock according to the received data strobe, generating three time points with a period of the data strobe clock, sampling the data at the three time points, to obtain three sampled data, determining whether to adjust positions of the three time points according to a comparison among the three sampled data, and configuring the valid data reception window according to the positions of the three time points when determining not to adjust the positions of the three time points.

Abstract: The present disclosure discloses a memory access interface device. The clock generation circuit thereof generates reference clocks. Each of the DDR access signal transmission circuits thereof, under a DDR mode, adjusts a phase and a duty cycle of one of DDR access signals according to one of DDR reference clock signals to generate one of output access signals to access the memory device. The data signal transmission circuit thereof, under an SDR mode, applies a minimum latency on an SDR data signal according to the command and address reference clock signal to generate an output SDR data signal to access the memory device. The command and address signal transmission circuit thereof, under either the DDR or SDR mode, applies a programmable latency on a command and address signal according to the command and address reference clock signal to generate an output command and address signal to access the memory device.

Abstract: A memory controller comprising: a delay circuit, configured to use a first delay value and a second delay value to respectively delay a sampling clock signal to generate a first and a second delayed sampling clock signal; a sampling circuit, configured to use a first edge of the first delayed sampling clock signal to sample a data signal to generate a first sampling value, and configured to use a second edge of the second delayed sampling clock signal to sample the data signal to generate a second sampling value; and a calibrating circuit, configured to generate a sampling delay value according to the first delay value based on the first sampling value and the second sampling value. The delay circuit uses the sampling delay value to generate an adjusted sampling clock signal and the sampling circuit sample the data signal by the adjusted sampling clock signal.

Abstract: A method of foreground auto-calibrating data reception window for a DRAM system is disclosed. The method comprises receiving data strobe and data from a DRAM of the DARM system, capturing a data strobe clock according to the received data strobe, generating three time points with a period of the data strobe clock, sampling the data at the three time points, to obtain three sampled data, determining whether to adjust positions of the three time points according to a comparison among the three sampled data, and configuring the valid data reception window according to the positions of the three time points when determining not to adjust the positions of the three time points.

Abstract: Disclosed is a DDR SDRAM physical layer interface circuit including: a multiphase clock generator generating a plurality of clocks including a reference clock, a first clock, a second clock and a third clock; a frequency dividing circuit generating a PHY clock according to the first clock; a clock output path outputting the reference clock to a storage circuit; a first output circuit outputting a first output signal to the storage circuit according to a first input signal of a memory controller, the first clock and the PHY clock; a second output circuit outputting a second output signal to the storage circuit according to a second input signal of the memory controller, the second clock and the PHY clock; and a third output circuit outputting a third output signal to the storage circuit according to a third input signal of the memory controller, the third clock and the PHY clock.

Abstract: Disclosed is a DDR SDRAM physical layer interface circuit including: a multiphase clock generator generating a plurality of clocks including a reference clock, a first clock, a second clock and a third clock; a frequency dividing circuit generating a PHY clock according to the first clock; a clock output path outputting the reference clock to a storage circuit; a first output circuit outputting a first output signal to the storage circuit according to a first input signal of a memory controller, the first clock and the PHY clock; a second output circuit outputting a second output signal to the storage circuit according to a second input signal of the memory controller, the second clock and the PHY clock; and a third output circuit outputting a third output signal to the storage circuit according to a third input signal of the memory controller, the third clock and the PHY clock.