Patents by Inventor Kuo-Wei Hong
Kuo-Wei Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088048Abstract: A chip structure provided herein includes a bridge structure including an interconnect bridge, a dielectric layer laterally surrounding the interconnect bridge and through dielectric vias extending from a top of the dielectric layer to a bottom of the dielectric layer, wherein a thickness of the interconnect bridge is identical to a height of each of the through dielectric vias; semiconductor dies disposed on the bridge structure, wherein each of the semiconductor dies overlaps both the interconnect bridge and the dielectric layer and is electrically connected to the interconnect bridge and at least one of the through dielectric vias; and a die support, the semiconductor dies being disposed between the die support and the bridge structure, wherein a sidewall of the die support is coplanar with a sidewall of the bridge structure.Type: ApplicationFiled: January 10, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chiang Ting, Jian-Wei Hong, Sung-Feng Yeh
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Publication number: 20240079364Abstract: Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.Type: ApplicationFiled: January 9, 2023Publication date: March 7, 2024Inventors: Chia-Hao Hsu, Jian-Wei Hong, Kuo-Chiang Ting, Sung-Feng Yeh
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Publication number: 20240079850Abstract: A semiconductor device includes a first contact layer, a second contact layer, an active layer, a photonic crystal layer, a passivation layer, a first electrode and a second electrode. The first contact layer has a first surface and a second surface opposite to each other. Microstructures are located on the second surface. The second contact layer is located below the first surface. The active layer is located between the first contact layer and the second contact layer. The photonic crystal layer is located between the active layer and the second contact layer. The passivation layer is located on the second contact layer. The first electrode is located on the passivation layer and is electrically connected the first surface of the first contact layer. The second electrode is located on the passivation layer and is electrically connected to the second contact layer.Type: ApplicationFiled: December 28, 2022Publication date: March 7, 2024Inventors: Wen-Cheng HSU, Yu-Heng HONG, Yao-Wei HUANG, Kuo-Bin HONG, Hao-Chung KUO
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Publication number: 20240079391Abstract: In an embodiment, a device includes: a first integrated circuit die comprising a semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first integrated circuit die, a surface of the gap-fill dielectric being substantially coplanar with an inactive surface of the semiconductor substrate and with a surface of the first through-substrate via; a dielectric layer on the surface of the gap-fill dielectric and the inactive surface of the semiconductor substrate; a first bond pad extending through the dielectric layer to contact the surface of the first through-substrate via, a width of the first bond pad being less than a width of the first through-substrate via; and a second integrated circuit die comprising a die connector bonded to the first bond pad.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Inventors: Chia-Hao Hsu, Jian-Wei Hong, Kuo-Chiang Ting, Sung-Feng Yeh
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Patent number: 8647722Abstract: A film forming cycle based on pulse CVD or ALD is repeated multiple times to form a single layer of insulation film, while a reforming cycle is implemented in the aforementioned process, either once or multiple times per each film forming cycle, by treating the surface of formed film using a treating gas that has been activated by a plasma.Type: GrantFiled: November 13, 2009Date of Patent: February 11, 2014Assignee: ASM Japan K.K.Inventors: Akiko Kobayashi, Akira Shimizu, Kuo-wei Hong, Nobuyoshi Kobayashi, Atsuki Fukazawa
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Patent number: 8415259Abstract: A method of forming a film on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which the semiconductor substrate is placed; introducing a precursor in pulses of less than 1.0-second duration into the reaction space wherein the reactive gas and the rare gas are introduced; exiting a plasma in pulses of less than 1.0-second duration immediately after the precursor is shut off; and maintaining the reactive gas and the rare gas as a purge of less than 2.0-second duration.Type: GrantFiled: March 2, 2012Date of Patent: April 9, 2013Assignee: ASM Japan K.K.Inventors: Woo Jin Lee, Kuo-Wei Hong, Akira Shimizu, Daekyun Jeong
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Patent number: 8394466Abstract: A method of forming a conformal dielectric film having Si—N bonds on a substrate having a patterned surface includes: introducing a reactant gas into a reaction space; introducing a silicon precursor in pulses of less than 5-second duration into the reaction space; applying a first RF power to the reaction space during the pulse of the silicon precursor; applying a second RF power to the reaction space during the interval of the silicon precursor pulse, wherein an average intensity of the second RF power during the interval of the silicon precursor pulse is greater than that of the first RF power during the pulse of the silicon precursor; and repeating the cycle to form a conformal dielectric film having Si—N bonds with a desired thickness on the patterned surface of the substrate.Type: GrantFiled: September 3, 2010Date of Patent: March 12, 2013Assignee: ASM Japan K.K.Inventors: Kuo-wei Hong, Akira Shimizu, Kunitoshi Namba, Woo-Jin Lee
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Patent number: 8334219Abstract: A method of forming stress-tuned dielectric films having Si—N bonds on a semiconductor substrate by modified plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen-and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space using a high frequency RF power source and a low frequency RF power source; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a stress-tuned dielectric film having Si—N bonds on the substrate.Type: GrantFiled: July 8, 2010Date of Patent: December 18, 2012Assignee: ASM Japan K.K.Inventors: Woo-Jin Lee, Kuo-Wei Hong, Akira Shimuzu
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Publication number: 20120220139Abstract: A method of forming a film on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which the semiconductor substrate is placed; introducing a precursor in pulses of less than 1.0-second duration into the reaction space wherein the reactive gas and the rare gas are introduced; exiting a plasma in pulses of less than 1.0-second duration immediately after the precursor is shut off; and maintaining the reactive gas and the rare gas as a purge of less than 2.0-second duration.Type: ApplicationFiled: March 2, 2012Publication date: August 30, 2012Applicant: ASM JAPAN K.K.Inventors: Woo-Jin Lee, Kuo-wei Hong, Akira Shimizu, Deakyun Jeong
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Patent number: 8173554Abstract: A method of forming dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which the semiconductor substrate is placed; introducing a hydrogen-containing silicon precursor in pulses of less than 1.0-second duration into the reaction space wherein the reactive gas and the rare gas are introduced; exiting a plasma in pulses of less than 1.0-second duration immediately after the silicon precursor is shut off; and maintaining the reactive gas and the rare gas as a purge of less than 2.0-second duration.Type: GrantFiled: October 8, 2010Date of Patent: May 8, 2012Assignee: ASM Japan K.K.Inventors: Woo Jin Lee, Kuo-Wei Hong, Akira Shimizu, Deakyun Jeong
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Publication number: 20120058282Abstract: A method of forming a conformal dielectric film having Si—N bonds on a substrate having a patterned surface includes: introducing a reactant gas into a reaction space; introducing a silicon precursor in pulses of less than 5-second duration into the reaction space; applying a first RF power to the reaction space during the pulse of the silicon precursor; applying a second RF power to the reaction space during the interval of the silicon precursor pulse, wherein an average intensity of the second RF power during the interval of the silicon precursor pulse is greater than that of the first RF power during the pulse of the silicon precursor; and repeating the cycle to form a conformal dielectric film having Si—N bonds with a desired thickness on the patterned surface of the substrate.Type: ApplicationFiled: September 3, 2010Publication date: March 8, 2012Applicant: ASM JAPAN K.K.Inventors: Kuo-wei Hong, Akira Shimizu, Kunitoshi Namba, Woo-Jin Lee
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Patent number: 8129291Abstract: A method of forming dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which the semiconductor substrate is placed; introducing a hydrogen-containing silicon precursor in pulses of less than 1.0-second duration into the reaction space wherein the reactive gas and the rare gas are introduced; exiting a plasma in pulses of less than 1.0-second duration immediately after the silicon precursor is shut off; and maintaining the reactive gas and the rare gas as a purge of less than 2.0-second duration.Type: GrantFiled: October 8, 2010Date of Patent: March 6, 2012Assignee: ASM Japan K.K.Inventors: Woo Jin Lee, Kuo-Wei Hong, Akira Shimizu, Deakyun Jeong
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Publication number: 20110086516Abstract: A method of forming dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which the semiconductor substrate is placed; introducing a hydrogen-containing silicon precursor in pulses of less than 1.0-second duration into the reaction space wherein the reactive gas and the rare gas are introduced; exiting a plasma in pulses of less than 1.0-second duration immediately after the silicon precursor is shut off; and maintaining the reactive gas and the rare gas as a purge of less than 2.0-second duration.Type: ApplicationFiled: October 8, 2010Publication date: April 14, 2011Applicant: ASM JAPAN K.K.Inventors: Woo Jin Lee, Kuo-wei Hong, Akira Shimizu, Deakyun Jeong
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Publication number: 20110014795Abstract: A method of forming stress-tuned dielectric films having Si—N bonds on a semiconductor substrate by modified plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen-and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space using a high frequency RF power source and a low frequency RF power source; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a stress-tuned dielectric film having Si—N bonds on the substrate.Type: ApplicationFiled: July 8, 2010Publication date: January 20, 2011Applicant: ASM JAPAN K.K.Inventors: Woo Jin Lee, Kuo-Wei Hong, Akira Shimizu
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Publication number: 20100124618Abstract: A film forming cycle based on pulse CVD or ALD is repeated multiple times to form a single layer of insulation film, while a reforming cycle is implemented in the aforementioned process, either once or multiple times per each film forming cycle, by treating the surface of formed film using a treating gas that has been activated by a plasma.Type: ApplicationFiled: November 13, 2009Publication date: May 20, 2010Applicant: ASM JAPAN K.K.Inventors: Akiko Kobayashi, Akira Shimizu, Kuo-wei Hong, Nobuyoshi Kobayashi, Atsuki Fukazawa