Patents by Inventor Kuo-Wei Peng

Kuo-Wei Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8487377
    Abstract: A MOSFET layout is disclosed. The MOSFET comprises a drain region, a gate region, a source region and a body region. The gate region is disposed outside the drain region and adjacent to the drain region. The source region has a plurality of source sections, which are disposed outside of the gate region and adjacent to the gate region. Each of two adjacent source sections has a source blank zone there between. The body region has at least two body portions, which are disposed at the source blank zones and adjacent to the gate region.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: July 16, 2013
    Assignee: Green Solution Technology Co., Ltd.
    Inventors: Chung-Che Yu, Kuo-Wei Peng, Li-Min Lee
  • Patent number: 8138557
    Abstract: A layout structure of a MOSFET is provided. The layout structure of the MOSFET includes a plurality of MOSFET cells, a first source/drain metal bus structure and a second source/drain metal bus structure. The first source/drain metal bus structure is electrically connected to first sources/drains of the MOSFET cells, and a width thereof is gradually decreased in a predetermined direction. The second source/drain metal bus structure is electrically connected to second sources/drains of the MOSFET cells, and a width thereof is gradually increased in the predetermined direction.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: March 20, 2012
    Assignee: Green Solution Technology Co., Ltd.
    Inventors: Kuo-Wei Peng, Zhong-Wei Liu, Qian-Hua Zhou
  • Publication number: 20120061771
    Abstract: A MOSFET layout is disclosed. The MOSFET comprises a drain region, a gate region, a source region and a body region. The gate region is disposed outside the drain region and adjacent to the drain region. The source region has a plurality of source sections, which are disposed outside of the gate region and adjacent to the gate region. Each of two adjacent source sections has a source blank zone there between. The body region has at least two body portions, which are disposed at the source blank zones and adjacent to the gate region.
    Type: Application
    Filed: April 25, 2011
    Publication date: March 15, 2012
    Applicant: GREEN SOLUTION TECHNOLOGY CO., LTD.
    Inventors: Chung-Che YU, Kuo-Wei PENG, Li-Min LEE
  • Publication number: 20110113397
    Abstract: A layout structure of a MOSFET is provided. The layout structure of the MOSFET includes a plurality of MOSFET cells, a first source/drain metal bus structure and a second source/drain metal bus structure. The first source/drain metal bus structure is electrically connected to first sources/drains of the MOSFET cells, and a width thereof is gradually decreased in a predetermined direction. The second source/drain metal bus structure is electrically connected to second sources/drains of the MOSFET cells, and a width thereof is gradually increased in the predetermined direction.
    Type: Application
    Filed: November 11, 2009
    Publication date: May 12, 2011
    Applicant: GREEN SOLUTION TECHNOLOGY CO., LTD.
    Inventors: Kuo-Wei Peng, Zhong-Wei Liu, Qian-Hua Zhou
  • Patent number: 7486103
    Abstract: A switching system capable of reducing the noise of the output signal is provided. The switching system includes a first switch and a second switch, wherein the first switch conducts a first signal according to a first control signal; the second switch conducts a second signal according to a second control signal. And the voltages of the first control signal and the second control signal are restricted within a voltage interval to reduce the noise produced during the switching of the switches.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: February 3, 2009
    Assignee: Young Lighting Technology Corporation
    Inventors: Shian-Sung Shiu, Chung-Che Yu, Kuo-Wei Peng
  • Patent number: 7439894
    Abstract: An electronic apparatus for current source array and the layout method thereof are provided. The current source array includes a low bit group and a plurality of high bit groups. The low bit group has a plurality of current source units and is disposed at a central block of a layout area. In addition, each of the high bit groups has a plurality of current source units respectively disposed at a plurality of peripheral blocks of the layout area.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: October 21, 2008
    Assignee: Beyond Innovation Technology Co., Ltd.
    Inventors: Kuo-Wei Peng, Shian-Sung Shiu
  • Patent number: 7429945
    Abstract: The invention relates to an analog-to-digital converter comprising a reference voltage generating circuit, two coarse/fine comparators and two encoders for encoding the comparison result of the two coarse/fine comparators. In the invention, the two coarse/fine comparators processes a coarse comparison procedure and a fine comparison procedure on an input voltage in different clock cycle, thus, a sampling voltage error caused by an error of sampling time decreases. In another aspect of the invention, the capacitance of the input capacitor of the analog-to-digital converter decreases because the comparators for coarse comparison and fine comparison are the same, thus, a large power amplifier is not required for driving the input capacitor.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: September 30, 2008
    Assignee: Beyond Innovation Technology Co., Ltd.
    Inventors: Shian-Sung Shiu, Kuo-Wei Peng
  • Publication number: 20080151118
    Abstract: A switching system capable of reducing the noise of the output signal is provided. The switching system includes a first switch and a second switch, wherein the first switch conducts a first signal according to a first control signal; the second switch conducts a second signal according to a second control signal. And the voltages of the first control signal and the second control signal are restricted within a voltage interval to reduce the noise produced during the switching of the switches.
    Type: Application
    Filed: April 12, 2007
    Publication date: June 26, 2008
    Applicant: BEYOND INNOVATION TECHNOLOGY CO., LTD.
    Inventors: SHIAN-SUNG SHIU, CHUNG-CHE YU, KUO-WEI PENG
  • Publication number: 20080111589
    Abstract: A driving adjustment circuit that increases the driving capability of amplifier by adding a driving current directly to an output stage of the amplifier is provided. The driving adjustment circuit adjusts the driving capability according to an external load. Thus, the present invention not only solves the problem of insufficient driving capability of a digital-to-analog converter, but also effectively reduces unnecessary high power consumption and improves the stability of the system by adjusting the driving capability of the amplifier according to the external load.
    Type: Application
    Filed: December 21, 2006
    Publication date: May 15, 2008
    Applicant: BEYOND INNOVATION TECHNOLOGY CO., LTD.
    Inventors: Shian-Sung Shiu, Kuo-Wei Peng
  • Publication number: 20080018512
    Abstract: An electronic apparatus for current source array and the layout method thereof are provided. The current source array includes a low bit group and a plurality of high bit groups. The low bit group has a plurality of current source units and is disposed at a central block of a layout area. In addition, each of the high bit groups has a plurality of current source units respectively disposed at a plurality of peripheral blocks of the layout area.
    Type: Application
    Filed: November 15, 2006
    Publication date: January 24, 2008
    Applicant: BEYOND INNOVATION TECHNOLOGY CO., LTD.
    Inventors: Kuo-Wei Peng, Shian-Sung Shiu
  • Publication number: 20070252742
    Abstract: The invention relates to an analog-to-digital converter comprising a reference voltage generating circuit, two coarse/fine comparators and two encoders for encoding the comparison result of the two coarse/fine comparators. In the invention, the two coarse/fine comparators processes a coarse comparison procedure and a fine comparison procedure on an input voltage in different clock cycle, thus, a sampling voltage error caused by an error of sampling time decreases. In another aspect of the invention, the capacitance of the input capacitor of the analog-to-digital converter decreases because the comparators for coarse comparison and fine comparison are the same, thus, a large power amplifier is not required for driving the input capacitor.
    Type: Application
    Filed: January 11, 2007
    Publication date: November 1, 2007
    Applicant: BEYOND INNOVATION TECHNOLOGY CO., LTD.
    Inventors: Shian-Sung Shiu, Kuo-Wei Peng