Abstract: A MOSFET layout is disclosed. The MOSFET comprises a drain region, a gate region, a source region and a body region. The gate region is disposed outside the drain region and adjacent to the drain region. The source region has a plurality of source sections, which are disposed outside of the gate region and adjacent to the gate region. Each of two adjacent source sections has a source blank zone there between. The body region has at least two body portions, which are disposed at the source blank zones and adjacent to the gate region.

Abstract: A layout structure of a MOSFET is provided. The layout structure of the MOSFET includes a plurality of MOSFET cells, a first source/drain metal bus structure and a second source/drain metal bus structure. The first source/drain metal bus structure is electrically connected to first sources/drains of the MOSFET cells, and a width thereof is gradually decreased in a predetermined direction. The second source/drain metal bus structure is electrically connected to second sources/drains of the MOSFET cells, and a width thereof is gradually increased in the predetermined direction.

Abstract: A MOSFET layout is disclosed. The MOSFET comprises a drain region, a gate region, a source region and a body region. The gate region is disposed outside the drain region and adjacent to the drain region. The source region has a plurality of source sections, which are disposed outside of the gate region and adjacent to the gate region. Each of two adjacent source sections has a source blank zone there between. The body region has at least two body portions, which are disposed at the source blank zones and adjacent to the gate region.

Abstract: A layout structure of a MOSFET is provided. The layout structure of the MOSFET includes a plurality of MOSFET cells, a first source/drain metal bus structure and a second source/drain metal bus structure. The first source/drain metal bus structure is electrically connected to first sources/drains of the MOSFET cells, and a width thereof is gradually decreased in a predetermined direction. The second source/drain metal bus structure is electrically connected to second sources/drains of the MOSFET cells, and a width thereof is gradually increased in the predetermined direction.

Abstract: A switching system capable of reducing the noise of the output signal is provided. The switching system includes a first switch and a second switch, wherein the first switch conducts a first signal according to a first control signal; the second switch conducts a second signal according to a second control signal. And the voltages of the first control signal and the second control signal are restricted within a voltage interval to reduce the noise produced during the switching of the switches.

Abstract: An electronic apparatus for current source array and the layout method thereof are provided. The current source array includes a low bit group and a plurality of high bit groups. The low bit group has a plurality of current source units and is disposed at a central block of a layout area. In addition, each of the high bit groups has a plurality of current source units respectively disposed at a plurality of peripheral blocks of the layout area.

Abstract: The invention relates to an analog-to-digital converter comprising a reference voltage generating circuit, two coarse/fine comparators and two encoders for encoding the comparison result of the two coarse/fine comparators. In the invention, the two coarse/fine comparators processes a coarse comparison procedure and a fine comparison procedure on an input voltage in different clock cycle, thus, a sampling voltage error caused by an error of sampling time decreases. In another aspect of the invention, the capacitance of the input capacitor of the analog-to-digital converter decreases because the comparators for coarse comparison and fine comparison are the same, thus, a large power amplifier is not required for driving the input capacitor.

Abstract: A switching system capable of reducing the noise of the output signal is provided. The switching system includes a first switch and a second switch, wherein the first switch conducts a first signal according to a first control signal; the second switch conducts a second signal according to a second control signal. And the voltages of the first control signal and the second control signal are restricted within a voltage interval to reduce the noise produced during the switching of the switches.

Abstract: A driving adjustment circuit that increases the driving capability of amplifier by adding a driving current directly to an output stage of the amplifier is provided. The driving adjustment circuit adjusts the driving capability according to an external load. Thus, the present invention not only solves the problem of insufficient driving capability of a digital-to-analog converter, but also effectively reduces unnecessary high power consumption and improves the stability of the system by adjusting the driving capability of the amplifier according to the external load.

Abstract: An electronic apparatus for current source array and the layout method thereof are provided. The current source array includes a low bit group and a plurality of high bit groups. The low bit group has a plurality of current source units and is disposed at a central block of a layout area. In addition, each of the high bit groups has a plurality of current source units respectively disposed at a plurality of peripheral blocks of the layout area.

Abstract: The invention relates to an analog-to-digital converter comprising a reference voltage generating circuit, two coarse/fine comparators and two encoders for encoding the comparison result of the two coarse/fine comparators. In the invention, the two coarse/fine comparators processes a coarse comparison procedure and a fine comparison procedure on an input voltage in different clock cycle, thus, a sampling voltage error caused by an error of sampling time decreases. In another aspect of the invention, the capacitance of the input capacitor of the analog-to-digital converter decreases because the comparators for coarse comparison and fine comparison are the same, thus, a large power amplifier is not required for driving the input capacitor.