Patents by Inventor Kuo-Wei WANG
Kuo-Wei WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978664Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.Type: GrantFiled: July 29, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
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Publication number: 20240145470Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: Lung-Kun CHU, Mao-Lin HUANG, Chung-Wei HSU, Jia-Ni YU, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Chih-Hao WANG
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Publication number: 20240130257Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.Type: ApplicationFiled: April 21, 2023Publication date: April 18, 2024Inventors: Fu-Hai LI, Yi Ching ONG, Hsin Heng WANG, Tsung-Hao YEH, Yu-Wei TING, Kuo-Pin CHANG, Hung-Ju LI, Kuo-Ching HUANG
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Patent number: 11961769Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.Type: GrantFiled: November 7, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
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Patent number: 11961913Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain feature on a semiconductor fin structure, a first isolation structure surrounding the semiconductor fin structure, source/drain spacers on the first isolation structure and surrounding a lower portion of the source/drain feature, a dielectric fin structure adjoining and in direct contact with the first isolation structure and one of the source/drain spacers, and an interlayer dielectric layer over the source/drain spacers and the dielectric fin structure and surrounding an upper portion of the source/drain feature.Type: GrantFiled: April 21, 2023Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Chiang, Shi-Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11961840Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.Type: GrantFiled: August 9, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240120402Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.Type: ApplicationFiled: November 19, 2023Publication date: April 11, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Ni YU, Kuo-Cheng CHIANG, Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Chun-Fu LU, Chih-Hao WANG, Kuan-Lun CHENG
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Publication number: 20240113195Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.Type: ApplicationFiled: February 22, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Ni YU, Lung-Kun CHU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
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Patent number: 11948987Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.Type: GrantFiled: September 9, 2020Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11948970Abstract: A semiconductor device includes a semiconductor fin, a gate structure, and a dielectric isolation plug. The semiconductor fin extends along a first direction above a substrate and includes a silicon germanium layer and a silicon layer over the silicon germanium layer. The gate structure extends across the semiconductor fin along a second direction perpendicular to the first direction. The dielectric isolation plug extends downwardly from a top surface of the silicon layer into the silicon germanium layer when viewed in a cross section taken along the first direction.Type: GrantFiled: December 2, 2019Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11942548Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.Type: GrantFiled: May 18, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Chih-Hao Wang, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11942145Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.Type: GrantFiled: May 6, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
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Publication number: 20240096818Abstract: Devices and method for forming a shielding assembly including a first chip package structure sensitive to magnetic interference (MI), a second chip package structure sensitive to electromagnetic interference (EMI), and a shield surrounding sidewalls and top surfaces of the first chip package structure and the second chip package structure, in which the shield is a magnetic shielding material. In some embodiments, the shield may include silicon steel, in some embodiments, the shield may include Mu-metal. The silicon-steel-based or Mu-metal-based shield may provide both EMI and MI protection to multiple chip package structures with various susceptibilities to EMI and MI.Type: ApplicationFiled: April 20, 2023Publication date: March 21, 2024Inventors: Harry-Hak-Lay Chuang, Yuan-Jen Lee, Kuo-An Liu, Ching-Huang Wang, C.T. Kuo, Tien-Wei Chiang
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Publication number: 20240096880Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.Type: ApplicationFiled: November 16, 2023Publication date: March 21, 2024Inventors: Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu
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Publication number: 20240098960Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Inventors: YU-KUAN LIN, CHANG-TA YANG, PING-WEI WANG, KUO-YI CHAO, MEI-YUN WANG
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Patent number: 11282197Abstract: The present disclosure provides an operating method of a system for analyzing brain tissue based on computerized tomographic imaging, and the operation method includes steps as follows. A computed tomography image of a subject is aligned to a predetermined standard brain space image, to obtain a first normalized test computed tomography image. A voxel contrast of the first normalized test computed tomography image is enhanced to obtain an enhanced first normalized test computed tomography image. The enhanced first normalized test computed tomography image is aligned to an average computed tomographic image of a control group to obtain a second normalized test computed tomography image. An analysis based on the second normalized test computed tomography image and a plurality of computerized tomographic images of the control group is performed to obtain a t-score map.Type: GrantFiled: July 14, 2020Date of Patent: March 22, 2022Assignees: National Central University, Taipei Medical University (TMU)Inventors: Syu-Jyun Peng, Yu-Wei Chen, Jing-Yu Yang, Jang-Zern Tsai, Kuo-Wei Wang, Yeh-Lin Kuo
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Publication number: 20210256688Abstract: The present disclosure provides an operating method of a system for analyzing brain tissue based on computerized tomographic imaging, and the operation method includes steps as follows. A computed tomography image of a subject is aligned to a predetermined standard brain space image, to obtain a first normalized test computed tomography image. A voxel contrast of the first normalized test computed tomography image is enhanced to obtain an enhanced first normalized test computed tomography image. The enhanced first normalized test computed tomography image is aligned to an average computed tomographic image of a control group to obtain a second normalized test computed tomography image. An analysis based on the second normalized test computed tomography image and a plurality of computerized tomographic images of the control group is performed to obtain a t-score map.Type: ApplicationFiled: July 14, 2020Publication date: August 19, 2021Inventors: Syu-Jyun PENG, Yu-Wei CHEN, Jing-Yu YANG, Jang-Zern TSAI, Kuo-Wei WANG, Yeh-Lin KUO
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Patent number: 11042983Abstract: The present disclosure provides an operating method of an automatic brain infarction detection system on magnetic resonance imaging (MRI), which includes steps as follows. Images corresponding to different slices of a brain of a subject are received from the MRI machine. The image mask process is performed on first and second images of the images. It is determined whether the cerebellum image intensity and the brain image intensity in the first image are matched. When the cerebellum image intensity and the brain image intensity are not matched, the cerebellar image intensity in the first image is adjusted. The first image is processed through a nonlinear regression to obtain a third image. A neural network identify an infarct region by using the first, second and third images that are cut.Type: GrantFiled: May 27, 2020Date of Patent: June 22, 2021Assignees: National Central University, Taipei Medical University (TMU)Inventors: Jang-Zern Tsai, Syu-Jyun Peng, Yu-Wei Chen, Meng-Zong Tsai, Kuo-Wei Wang, Yeh-Lin Kuo
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Patent number: 9466105Abstract: A magnetic resonance imaging white matter hyperintensities region recognizing method and system are disclosed herein. The white matter hyperintensities region recognizing method includes receiving and storing a FLAIR MRI image, a spin-lattice relaxation time weighted MRI image, and a diffusion weighted MRI image. Registration and fusion are preformed, and a white matter mask is determined. An intersection image of the FLAIR MRI image and the white matter mask is taken, a first region is determined after normalizing the intersection image, a cerebral infarct region is removed from the first image through the diffusion weighted MRI image, and then a determination is made as to whether to remove a remaining region in order to form a white matter hyperintensities region in the FLAIR MRI image.Type: GrantFiled: May 18, 2015Date of Patent: October 11, 2016Assignees: National Central UniversityInventors: Syu-Jyun Peng, Yu-Wei Chen, Jang-Zern Tsai, Kuo-Wei Wang
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Patent number: 9412163Abstract: A method for detecting a cerebral infarct includes receiving an image of a brain of a subject from a magnetic resonance imaging scanner, wherein the image has a plurality of voxels, and each of the voxels has a voxel intensity. Then, the voxel intensities are normalized, wherein the normalized voxel intensities have a distribution peak, and the normalized voxel intensity of the distribution peak is Ipeak. A threshold is determined, which is the Ipeak+ a value. Voxel having the normalized voxel intensity larger than the threshold is selected, wherein the selected voxel is the cerebral infarct. A method for quantifying the cerebral infarct is also provided.Type: GrantFiled: March 10, 2015Date of Patent: August 9, 2016Assignees: National Central UniversityInventors: Syu-Jyun Peng, Jang-Zern Tsai, Yu-Wei Chen, Kuo-Wei Wang