Patents by Inventor Kuo-Wei Yeh
Kuo-Wei Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130257Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.Type: ApplicationFiled: April 21, 2023Publication date: April 18, 2024Inventors: Fu-Hai LI, Yi Ching ONG, Hsin Heng WANG, Tsung-Hao YEH, Yu-Wei TING, Kuo-Pin CHANG, Hung-Ju LI, Kuo-Ching HUANG
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Publication number: 20240088048Abstract: A chip structure provided herein includes a bridge structure including an interconnect bridge, a dielectric layer laterally surrounding the interconnect bridge and through dielectric vias extending from a top of the dielectric layer to a bottom of the dielectric layer, wherein a thickness of the interconnect bridge is identical to a height of each of the through dielectric vias; semiconductor dies disposed on the bridge structure, wherein each of the semiconductor dies overlaps both the interconnect bridge and the dielectric layer and is electrically connected to the interconnect bridge and at least one of the through dielectric vias; and a die support, the semiconductor dies being disposed between the die support and the bridge structure, wherein a sidewall of the die support is coplanar with a sidewall of the bridge structure.Type: ApplicationFiled: January 10, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chiang Ting, Jian-Wei Hong, Sung-Feng Yeh
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Publication number: 20240090234Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Te-Wei Yeh, Chien-Liang Wu
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Publication number: 20240079391Abstract: In an embodiment, a device includes: a first integrated circuit die comprising a semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first integrated circuit die, a surface of the gap-fill dielectric being substantially coplanar with an inactive surface of the semiconductor substrate and with a surface of the first through-substrate via; a dielectric layer on the surface of the gap-fill dielectric and the inactive surface of the semiconductor substrate; a first bond pad extending through the dielectric layer to contact the surface of the first through-substrate via, a width of the first bond pad being less than a width of the first through-substrate via; and a second integrated circuit die comprising a die connector bonded to the first bond pad.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Inventors: Chia-Hao Hsu, Jian-Wei Hong, Kuo-Chiang Ting, Sung-Feng Yeh
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Publication number: 20240079364Abstract: Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.Type: ApplicationFiled: January 9, 2023Publication date: March 7, 2024Inventors: Chia-Hao Hsu, Jian-Wei Hong, Kuo-Chiang Ting, Sung-Feng Yeh
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Publication number: 20240038978Abstract: The present invention provides a titanium-niobium composite oxide, which includes titanium, niobium, dopant M and oxygen, and the molar ratio of the titanium, niobium and dopant M is 1:(2?x):x, and x is 0.01 to 0.2; wherein the dopant M is doped in a crystal structure with a monoclinic crystal structure formed from the titanium, niobium and oxygen, and the dopant M is at least one metal element selected from the group consisting of Sn, Al and Zr. The present invention further provides a preparation method of the titanium-niobium composite oxide, an active material and a lithium ion secondary battery using the same. The titanium-niobium composite oxide produced by the present invention has better electrical performance than the existing negative electrode materials, so that the lithium ion secondary battery using it can exhibit longer cycle life, larger electric capacity and faster charging and discharging performance, thereby having a bright prospect of the application.Type: ApplicationFiled: February 6, 2023Publication date: February 1, 2024Applicant: GUS TECHNOLOGY CO., LTD.Inventors: Chung-Chieh CHANG, Kuo-Wei YEH, Wen-Chia HSU, Jia-Hui WANG, Chia-Huan CHUNG, Dong-Ze WU, PREM CHANDAN DEVANGA
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Patent number: 11177540Abstract: A method for manufacturing a negative tab of a pouch cell includes following step of cleaning and surface roughening a copper foil substrate, plating a nickel film, cleaning and surface roughening the nickel film, plating a passivated metal film and cleaning and surface roughening the passivated metal film. A method for manufacturing a positive tab of a pouch cell includes following step of cleaning and surface roughening an aluminum foil substrate, plating a passivated metal film and cleaning and surface roughening the passivated metal film.Type: GrantFiled: October 1, 2018Date of Patent: November 16, 2021Inventors: Chung-Chieh Chang, Kuo-Wei Yeh
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Publication number: 20200335779Abstract: A method of producing the spherical precursor containing lithium ions as cathode material for lithium-ion battery, which includes the following steps. The metal salts containing lithium ions and acid radicals and water are thoroughly mixed to form an aqueous metal salt solution containing lithium ions. The aqueous metal salt solution containing lithium ions is fed into the hot-blast furnace chamber for the high temperature spray granulating equipment, and the atomizer sprays the aqueous metal salt solution containing lithium ions in the hot-blast furnace chamber, so as to form spherical liquid drops in particle size of 0.1 ?m to 20 ?m. The hot air at 300° C. to 1000° C. is supplied to the hot-blast furnace chamber, so that the atomized spherical liquid drops and hot air generate pyrolysis effect to pyrolyze the acid radicals, and the spherical liquid drops are dried instantaneously to form the spherical precursor containing lithium ions.Type: ApplicationFiled: April 18, 2019Publication date: October 22, 2020Inventors: Chung-Chieh CHANG, Kuo-Wei YEH
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Publication number: 20190165352Abstract: A method for manufacturing a negative tab of a pouch cell includes following step of cleaning and surface roughening a copper foil substrate, plating a nickel film, cleaning and surface roughening the nickel film, plating a passivated metal film and cleaning and surface roughening the passivated metal film. A method for manufacturing a positive tab of a pouch cell includes following step of cleaning and surface roughening an aluminum foil substrate, plating a passivated metal film and cleaning and surface roughening the passivated metal film.Type: ApplicationFiled: October 1, 2018Publication date: May 30, 2019Inventors: Chung-Chieh CHANG, Kuo-Wei YEH
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Patent number: 10104288Abstract: A vertex processing device applied in an image processing system having an image capture module is disclosed. The image capture module generates camera images. The vertex processing device comprises a coefficient interpolation unit and a coordinate modifying unit. The coefficient interpolation unit generates an interpolated warping coefficient for each camera image with respect to each vertex from a vertex list based on n number of warping coefficients and its original texture coordinates in each camera image. The coordinate modifying unit calculates modified texture coordinates in each camera image for each vertex according to the interpolated warping coefficient and its original texture coordinates in each camera image. The vertex list comprises vertices with data structures that define vertex mapping between the camera images and a panoramic image. The n number of warping coefficients correspond to n number of overlap regions in the panoramic image.Type: GrantFiled: February 8, 2017Date of Patent: October 16, 2018Assignee: ASPEED TECHNOLOGY INC.Inventors: Pei-Hen Hung, Chung-Yen Lu, Kuo-Wei Yeh, Jing-Chuan Chen
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Publication number: 20180227484Abstract: A vertex processing device applied in an image processing system having an image capture module is disclosed. The image capture module generates camera images. The vertex processing device comprises a coefficient interpolation unit and a coordinate modifying unit. The coefficient interpolation unit generates an interpolated warping coefficient for each camera image with respect to each vertex from a vertex list based on n number of warping coefficients and its original texture coordinates in each camera image. The coordinate modifying unit calculates modified texture coordinates in each camera image for each vertex according to the interpolated warping coefficient and its original texture coordinates in each camera image. The vertex list comprises vertices with data structures that define vertex mapping between the camera images and a panoramic image. The n number of warping coefficients correspond to n number of overlap regions in the panoramic image.Type: ApplicationFiled: February 8, 2017Publication date: August 9, 2018Inventors: Pei-Hen HUNG, Chung-Yen LU, KUO-WEI YEH, Jing-Chuan CHEN
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Patent number: 9471956Abstract: An embodiment of a graphic remoting system of the present invention includes a network, a server and a client device. The network is applied to a RDP protocol. The server transfers display rendering commands which indicates a destination region through the network. The client device receives the display rendering commands. The client device of the present invention includes at least a graphic render engine, at least a surface, at least a mask generator, a plurality of mask buffer, at least a direct memory access with masks, and a plurality of display buffers. The surface is used for storing an image. The graphic render engine generates the image and stores the image into the surface according to the destination region. The mask buffers is used for storing bit masks; wherein the content values of the mask buffers are indicating updated areas of the image stored in the surface. The mask generator generates the bit masks according to the destination region, and stores the bit masks into the mask buffers.Type: GrantFiled: August 29, 2014Date of Patent: October 18, 2016Assignee: ASPEED TECHNOLOGY INC.Inventors: Chung-Yen Lu, Kuo-Wei Yeh, Ming-Chi Bai, Lung-Hsiang Kai
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Publication number: 20160063667Abstract: An embodiment of a graphic remoting system of the present invention includes a network, a server and a client device. The network is applied to a RDP protocol. The server transfers display rendering commands which indicates a destination region through the network. The client device receives the display rendering commands. The client device of the present invention includes at least a graphic render engine, at least a surface, at least a mask generator, a plurality of mask buffer, at least a direct memory access with masks, and a plurality of display buffers. The surface is used for storing an image. The graphic render engine generates the image and stores the image into the surface according to the destination region. The mask buffers is used for storing bit masks; wherein the content values of the mask buffers are indicating updated areas of the image stored in the surface. The mask generator generates the bit masks according to the destination region, and stores the bit masks into the mask buffers.Type: ApplicationFiled: August 29, 2014Publication date: March 3, 2016Inventors: Chung-Yen LU, Kuo-Wei YEH, MING-CHI BAI, LUNG-HSIANG KAI
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Patent number: 9129581Abstract: A method and apparatus for displaying images is disclosed. The method of the invention includes the steps of: transferring a content of a first one of the display buffers to the display device; overwriting a second one of the display buffers with first image data, wherein the first image data represent data of updated pixels between two corresponding adjacent frames; obtaining a bit-map mask according to the updated pixels, wherein the bit-map mask indicates altered pixels for the two corresponding adjacent frames; and, then overwriting the second one of the display buffers with second image data from the other display buffers according to at least one bit-map mask.Type: GrantFiled: November 6, 2012Date of Patent: September 8, 2015Assignee: ASPEED TECHNOLOGY INC.Inventors: Kuo-Wei Yeh, Chung-Yen Lu
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Publication number: 20140125685Abstract: A method and apparatus for displaying images is disclosed. The method of the invention includes the steps of: transferring a content of a first one of the display buffers to the display device; overwriting a second one of the display buffers with first image data, wherein the first image data represent data of updated pixels between two corresponding adjacent frames; obtaining a bit-map mask according to the updated pixels, wherein the bit-map mask indicates altered pixels for the two corresponding adjacent frames; and, then overwriting the second one of the display buffers with second image data from the other display buffers according to at least one bit-map mask.Type: ApplicationFiled: November 6, 2012Publication date: May 8, 2014Applicant: ASPEED TECHNOLOGY INC.Inventors: Kuo-Wei YEH, Chung-Yen LU
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Patent number: 8663848Abstract: Disclosed is a C2/m-structured cathode material for a lithium-ion battery. The cathode material includes a lithium transition metal oxide represented by a formula of: Li(LiwNixCoyMnz)O2, wherein w+x+y+z=1, 0.42?z?0.60, 0.30?x+y?0.55, any of w, x, and y is larger than 0, and the cathode material having a single-phase structure with a space group of C2/m. A lithium-ion battery containing the C2/m-structured cathode material is also disclosed.Type: GrantFiled: November 15, 2011Date of Patent: March 4, 2014Assignees: LICO Technology Corp., Academia SinicaInventors: Maw-Kuen Wu, Tzu-Wen Huang, Horng-Yi Tang, Hua-Shu Chang, Chui-Chang Chiu, Kuo-Wei Yeh, Chung-Chieh Chang
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Publication number: 20130092695Abstract: A cookware is revealed. The cookware includes a pot having a receiving space with an opening facing upward. An upper edge of the pot extends outward and downward to form a pendent edge. Thus a heat storage space is formed between the pendent edge and a pot wall. While heating the pot, heat is accumulated and stored in the heat storage space so that cooking temperature is increased and cooking time is reduced. Therefore energy-saving is achieved.Type: ApplicationFiled: October 14, 2011Publication date: April 18, 2013Inventor: KUO-WEI YEH
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Publication number: 20120258364Abstract: Disclosed is a C2/m-structured cathode material for a lithium-ion battery. The cathode material includes a lithium transition metal oxide represented by a formula of: Li(LiwNixCoyMnz)O2, wherein w+x+y+z=1, 0.42?z?0.60, 0.30?x+y?0.55, any of w, x, and y is larger than 0, and the cathode material having a single-phase structure with a space group of C2/m. A lithium-ion battery containing the C2/m-structured cathode material is also disclosed.Type: ApplicationFiled: November 15, 2011Publication date: October 11, 2012Inventors: Maw-Kuen WU, Tzu-Wen HUANG, Horng-Yi TANG, Hua-Shu CHANG, Chui-Chang CHIU, Kuo-Wei YEH, Chung-Chieh CHANG
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Patent number: 6910059Abstract: An apparatus for calculating an exponential calculating result for a base 2 floating-point number comprises a transforming device, K exponential tables and a multiplier. The transforming device receives the floating-point number, transforms the floating-point number to an integer part and a fractional part and outputs the integer part and the fractional part. The fractional part is an N-bit number and divided into K parts which have N1, N2, . . . , NK bits respectively, wherein N=N1+N2+ . . . +NK. Each of the exponential tables receives one of the K parts divided from the fractional part and outputs a result. The multiplier receives all results from the exponential tables and outputs a mantissa. The integer part outputted form the transforming device is an exponent.Type: GrantFiled: July 9, 2002Date of Patent: June 21, 2005Assignee: Silicon Integrated Systems Corp.Inventors: Chung-Yen Lu, Kuo-Wei Yeh
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Patent number: 6845414Abstract: An apparatus and method for controlling an asynchronous First-In-First-Out (FIFO) memory. The asynchronous FIFO has separate, free running read and write clocks. A number of n-bit circular Gray code counters are used to handshake the operation between read and write parts of the FIFO, wherein n is any integer more than one. Additional binary counters are used to accumulate the read and write overflows for the circular Gray code counters. When any circular Gray code counter is overflow, the read or write count is transferred to the respective binary counter for recording the FIFO accesses.Type: GrantFiled: March 15, 2002Date of Patent: January 18, 2005Assignee: Silicon Integrated Systems Corp.Inventors: Fu-Chou Hsu, Kuo-Wei Yeh