Abstract: A semiconductor device includes a first type of light sensing units, where each instance of the first type of light sensing units is operable to receive a first amount of radiation; and a second type of light sensing units, where each instance of the second type of light sensing units is operable to receive a second amount of radiation, and the second type of light sensing units is arranged in an array with the first type of light sensing units to form a pixel sensor. The first amount of radiation is smaller than the second amount of radiation, and at least a first instance of the first type of light sensing units is adjacent to a second instance first type of light sensing unit.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

Abstract: An integrated gate driver circuit includes a control circuit, a plurality of drive stages and a plurality of discharge transistors. The control circuit is configured to output a plurality of clock signals within a frame period and to output a discharge enabling signal within a blanking period of the frame period. Each of the drive stages receives the clock signals and includes an output terminal configured to output a gate driving signal. Each of the discharge transistors is coupled to the output terminal of one of the drive stages and discharges the output terminal according to the discharge enabling signal thereby eliminating the voltage fluctuation of the output terminal in the blanking period.

Abstract: A gate driver is used to drive scan lines, a first scan line to a mth scan line. The m is a positive integer. The gate driver comprises driver units, a first driver unit to a mth driver unit, coupled with the first scan line to the mth scan line respectively. The driver units generate scan signals, a first scan signal to a mth scan signal, to drive the first scan line to the mth scan line respectively. The first driver unit, the second driver unit, the (m?1)th driver unit and the mth driver unit have the same circuit structure. The third driver unit and the (m?2)th driver unit have the same circuit structure. The fourth driver unit and the (m?3)th driver unit have the same circuit structure.

Abstract: An integrated gate driver circuit includes a control circuit, a plurality of drive stages and a plurality of discharge transistors. The control circuit is configured to output a plurality of clock signals within a frame period and to output a discharge enabling signal within a blanking period of the frame period. Each of the drive stages receives the clock signals and includes an output terminal configured to output a gate driving signal. Each of the discharge transistors is coupled to the output terminal of one of the drive stages and discharges the output terminal according to the discharge enabling signal thereby eliminating the voltage fluctuation of the output terminal in the blanking period.

Abstract: An integrated gate driver circuit includes a control circuit, a plurality of drive stages and a plurality of discharge transistors. The control circuit is configured to output a plurality of clock signals within a frame period and to output a discharge enabling signal within a blanking period of the frame period. Each of the drive stages receives the clock signals and includes an output terminal configured to output a gate driving signal. Each of the discharge transistors is coupled to the output terminal of one of the drive stages and discharges the output terminal according to the discharge enabling signal thereby eliminating the voltage fluctuation of the output terminal in the blanking period.