Abstract: A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of pads disposed on the active surface and electrically connected to the optical component; the pad extension traces are electrically connected to the pads; the via holes are formed through the chip and electrically connected to the pad extension traces; the lid is attached on the active surface of the chip; and the plurality of metal traces are disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defines a plurality of solder pads thereon.

Abstract: The present invention provides methods and apparatuses for a multi symptom test system. The multi symptom test apparatus having a plurality of zones for testing a plurality of conditions comprises the plurality of zones configured to receive a test sample wherein the zones responsive to the test sample provides a result indicative of a particular vaginitis test result.

Abstract: A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of pads disposed on the active surface and electrically connected to the optical component; the pad extension traces are electrically connected to the pads; the via holes are formed through the chip and electrically connected to the pad extension traces; the lid is attached on the active surface of the chip; and the plurality of metal traces are disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defines a plurality of solder pads thereon.

Abstract: A semiconductor package structure comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surface; pad extension traces are electrically connected to the pads; the via holes penetrate the chip and are electrically connected to the pad extension traces and exposed out of side surfaces of the semiconductor package structure; the lid is adhered onto the active surface of the chip; and the plurality of metal traces is disposed on the back surface of the chip, electrically connected to the plurality of via holes, and used to define a plurality of solder pads thereon. The present invention also provides a method for manufacturing the semiconductor package structure.

Abstract: A semiconductor package structure comprises a chip, a plurality of via holes, a lid, an adhesive ring and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surfaces; the via holes penetrate the chip and are electrically connected to the pads; the lid is adhered onto the active surface of the chip by the adhesive ring such that the adhesive ring surrounds the optical component; and the plurality of metal traces is disposed on the back surface of the chip, electrically connected to the plurality of via holes, and used to define a plurality of solder pads thereon. The present invention also provides a method for manufacturing the semiconductor package structure.