Abstract: The present invention discloses a network processor for a broadband gateway. The network processor includes a host processor; a plurality of networking interfaces, corresponding to a plurality of networking technologies, respectively; and a network address translation (NAT) engine, for accelerating packet processing from a first networking interface to a second networking interface.

Abstract: The present invention discloses a network processor for a broadband gateway. The network processor includes a host processor; a plurality of networking interfaces, corresponding to a plurality of networking technologies, respectively; and a network address translation (NAT) engine, for accelerating packet processing from a first networking interface to a second networking interface.

Abstract: A packet processing accelerator comprises a programmable packet classification module, a programmable flow control module, and a programmable packet header modification module. The programmable packet classification module is configured to receive a data packet and generate a start location of each protocol header of the data packet and a first index. The first index indicates classification of the data packet. The programmable flow control module is configured to generate a code of an output port and an action code according to the start location of each protocol header of the data packet and the first index. The programmable packet header modification module is configured to modify content of a plurality of protocol headers of the data packet according to the action code and to send the modified data packet to an output port according to the code of the output port.

Abstract: An architecture according to the present invention performs arithmetic operations on a composite field over dual basis. The ground field arithmetic is performed under dual basis. Therefore, the proposed architectures has the advantages of both composite field and dual basis processing, area efficiency and timing efficiency. Moreover, if the ground field GF(2n) arithmetic is implemented by bit-serial operation, the overall throughput of the composite field GF((2n)k) arithmetic will be twice than the one implemented in the finite field GF(2m)m=nk).

Abstract: A shared memory based network having a transferring network switch and a receiving network switch. In this network, each network switch has a stack, queues corresponding to output ports and a dared control port. The stack stores available buffer addresses of the shared memory. Each of the queues stores to-be-accessed buffer addresses of the corresponding output port. The shared control port is driven to indicate states of the shared memory based network, so that th stack of the transferring network switch is identical with the stack of the receiving network switch. The shared memory can be read by all output ports of both the transferring network switch and the receiving network switch according to their corresponding queues.

Abstract: A shared memory management mechanism and method for a high-speed network releases network packets efficiently and maintains the requirement of First In First Out. A series of linked lists including a linked list for each output queue and a linked list of used broadcast packets aids a buffer manager in efficiently managing the buffers in the shared memory. The linked lists include a special data format that encodes the broadcast status, links, and whether the next entry in the list is for unicast or broadcast frames. A scanning procedure scans the broadcast status to efficiently release the broadcast frame buffers. A dynamic scanning procedure consumes less bandwidth than the scanning procedure to efficiently release the broadcast frame buffers.

Abstract: A scheme for arbitrating access to a data bus shared among a plurality of competing sources is provided. Each competing source is assigned an adjustable priority weighting value (PWV) which is initially set to an initial value based on the bandwidth requirements of the competing source. During arbitration, the PWVs of those competing sources requesting access to the bus are compared, and the competing source with the smallest PWV is granted access. The PWV of the competing source which was granted access to the bus is reset to its initial value and the PWV of each competing source which requested, but was denied, access is reduced by one for subsequent comparisons. The arbitration scheme of the present invention is further applied to two-level arbitration. Each competing source is classified into a competing source group, and the requests from the grouped competing sources are processed by first level arbitration. First level arbitration passes one competing source for each group to a second level arbiter.