Patents by Inventor Kuo-Yen Liu

Kuo-Yen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10820945
    Abstract: A system includes an image capturing device, a subject reference marker disposed adjacent to a subject, a tool reference marker disposed on a treatment tool, a display device mounted on an operator, an operator reference marker disposed on the display device, and a processor. The image capturing device includes two image capturing modules that simultaneously and respectively capture two images of the operator, the subject, and the treatment tool. The processor receives the images, analyzes the images to obtain spatial locations of the reference markers, and transmits coordinate information and auxiliary information.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: November 3, 2020
    Assignees: CHANG GUNG UNIVERSITY
    Inventors: Hao-Li Liu, Shin-Yan Chiou, Chen-Yuan Liao, Wen-Yen Lin, Pin-Yuan Chen, Kuo-Chen Wei
  • Patent number: 10811377
    Abstract: A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 ?m to about 3 ?m. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Patent number: 10777510
    Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Publication number: 20200279944
    Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
  • Publication number: 20200211957
    Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.
    Type: Application
    Filed: March 6, 2020
    Publication date: July 2, 2020
    Inventors: Kuo-Yen LIU, Boo YEH, Min-Chang LIANG, Jui-Yao LAI, Sai-Hooi YEONG, Ying-Yan CHEN, Yen-Ming CHEN
  • Patent number: 10658510
    Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
  • Publication number: 20200152506
    Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Yu-Sheng TANG, Fu-Chen CHANG, Cheng-Lin HUANG, Wen-Ming CHEN, Chun-Yen LO, Kuo-Chio LIU
  • Patent number: 10629527
    Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yen Liu, Boo Yeh, Min-Chang Liang, Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen, Yen-Ming Chen
  • Publication number: 20200105654
    Abstract: A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.
    Type: Application
    Filed: June 21, 2019
    Publication date: April 2, 2020
    Inventors: Ling-Wei Li, Cheng-Lin Huang, Min-Tar Liu, Fu-Kang Chiao, Matt Chou, Chun-Yen Lo, Che-Jung Chu, Wen-Ming Chen, Kuo-Chio Liu
  • Patent number: 10535554
    Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Sheng Tang, Fu-Chen Chang, Cheng-Lin Huang, Chun-Yen Lo, Wen-Ming Chen, Kuo-Chio Liu
  • Publication number: 20200006545
    Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
  • Publication number: 20190328462
    Abstract: A system includes an image capturing device, a subject reference marker disposed adjacent to a subject, a tool reference marker disposed on a treatment tool, a display device mounted on an operator, an operator reference marker disposed on the display device, and a processor. The image capturing device includes two image capturing modules that simultaneously and respectively capture two images of the operator, the subject, and the treatment tool. The processor receives the images, analyzes the images to obtain spatial locations of the reference markers, and transmits coordinate information and auxiliary information.
    Type: Application
    Filed: November 2, 2018
    Publication date: October 31, 2019
    Inventors: Hao-Li LIU, Shin-Yan CHIOU, Chen-Yuan LIAO, Wen-Yen LIN, Pin-Yuan CHEN, Kuo-Chen WEI
  • Publication number: 20190324184
    Abstract: A light-emitting module structure includes a substrate, a plurality of light-emitting diodes (LEDs) disposed on the substrate, and a light-guiding layer covering the light-emitting diodes. The light-guiding layer has an upper surface, the upper surface has a plurality of recesses, and the recesses are above the light-emitting diodes or between the light-emitting diodes. This light-emitting module structure can improve the brightness and uniformity of the light-emitting module.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 24, 2019
    Inventors: Pei-Song CAI, Lung-Kuan LAI, Shih-Yu YEH, Guan-Zhi CHEN, Hong-Zhi LIU, Kuo-Yen CHANG, Ching-Hua LI
  • Publication number: 20190189577
    Abstract: A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 ?m to about 3 ?m. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.
    Type: Application
    Filed: November 19, 2018
    Publication date: June 20, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • Patent number: 10269697
    Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yen Liu, Boo Yeh, Min-Chang Liang, Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen, Yen-Ming Chen
  • Publication number: 20190109087
    Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.
    Type: Application
    Filed: November 20, 2018
    Publication date: April 11, 2019
    Inventors: Kuo-Yen LIU, Boo YEH, Min-Chang LIANG, Jui-Yao LAI, Sai-Hooi YEONG, Ying-Yan CHEN, Yen-Ming CHEN
  • Patent number: 10157826
    Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yen Liu, Boo Yeh, Min-Chang Liang, Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen, Yen-Ming Chen
  • Publication number: 20180151511
    Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
    Type: Application
    Filed: January 3, 2017
    Publication date: May 31, 2018
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Publication number: 20170186686
    Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 29, 2017
    Inventors: Kuo-Yen LIU, Boo YEH, Min-Chang LIANG, Jui-Yao LAI, Sai-Hooi YEONG, Ying-Yan CHEN, Yen-Ming CHEN
  • Patent number: 6835649
    Abstract: Within a method for forming a microelectronic fabrication there is provided a substrate having formed thereover a patterned dielectric layer which defines a via. There is also formed within a lower portion of the via a tungsten stud layer having a recess thereabove within the via. There is also formed within the recess a patterned conductor capping layer formed of a conductor material other than tungsten. The patterned conductor capping layer may seal a void formed within the tungsten stud layer.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: December 28, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Wei-Cheng Lee, Wen-Chen Chien, Yu-Da Fan, Kuo-Yen Liu, Yu-Ching Chang