Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view. The first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view. A second substrate is disposed over the first substrate and includes a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view. The second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.

Abstract: The present disclosure for wafer bonding, including forming an epitaxial layer on a top surface of a first wafer, forming a sacrificial layer over the epitaxial layer, trimming an edge of the first wafer, removing the sacrificial layer, forming an oxide layer over the top surface of the first wafer subsequent to removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer.

Abstract: A method includes forming an integrated circuit device on a semiconductor substrate, forming a through-via penetrating through the semiconductor substrate, and forming dummy patterns surrounding the through-via. The dummy patterns include a first plurality of dummy patterns having a first pattern density, and a second plurality of dummy patterns. The first plurality of dummy patterns are between the through-via and the second plurality of dummy patterns. The second plurality of dummy patterns have a second pattern density different from the first pattern density.

Abstract: A composite material and a method for manufacturing the composite material are provided. The composite material includes a laminated structure formed by co-extruding a thermoplastic elastomer and a modified thermoplastic elastomer. The use of the thermoplastic elastomer and the modified thermoplastic elastomer in the composite material can significantly reduce emissions during the manufacturing process, and the manufacturing process is simple and stable, and can improve the wear resistance of the composite material.

Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.

Abstract: A method includes finding a first plurality of through-silicon vias from a first layout of a wafer, and finding a second plurality of through-silicon vias from the first plurality of through-silicon vias. The second plurality of through-silicon vias are connected in parallel. The second plurality of through-silicon vias are merged into a large through-silicon via to generate a second layout of the wafer.

Abstract: A dynamic dispatching method for semiconductor manufacturing system relates to a dynamic dispatching rule based on self-organization for dispatching in a semiconductor manufacturing system, including S1: setting roles and parameters of self-organization units, and defining key nodes in a production environment; S2: constructing a negotiation mechanism between the self-organization units, and designing a decision-making and dispatching subject ESOU; S3: according to a decision instruction of the ESOU, designing a LSOU allocation dispatching unit for distinguishing single-batch processing and multi-batch processing; and S4: designing a dispatching mechanism based on the self-organization units to implement dynamic semiconductor dispatching. The dynamic dispatching method includes three aspects: role definitions of self-organization units, a negotiation mechanism between the self-organization units and a decision-making method thereof.

Abstract: The present invention provides a professional dance evaluation method for implementing Human Pose Estimation based on Deep Transfer Learning. First of all, the Transfer Learning principle of deep learning is combined with the pose features of professional dance training to build a Human Pose Estimation model. Afterwards, the video of demonstration dancing actions is collected and imported into the Human Pose Estimation model to obtain the time-dependent body keypoint data as the reference standard for evaluation. Finally, the video of the examinee's dancing actions is collected and imported into the Human Pose Estimation model to obtain the body keypoint data of the examinee's dancing actions, the similarity between it and the reference standard for evaluation is used for evaluating the standard level of dancing pose.

Abstract: The present invention provides a professional dance evaluation method for implementing Human Pose Estimation based on Deep Transfer Learning. First of all, the Transfer Learning principle of deep learning is combined with the pose features of professional dance training to build a Human Pose Estimation model. Afterwards, the video of demonstration dancing actions is collected and imported into the Human Pose Estimation model to obtain the time-dependent body keypoint data as the reference standard for evaluation. Finally, the video of the examinee's dancing actions is collected and imported into the Human Pose Estimation model to obtain the body keypoint data of the examinee's dancing actions, the similarity between it and the reference standard for evaluation is used for evaluating the standard level of dancing pose.

Abstract: A dynamic dispatching method for semiconductor manufacturing system relates to a dynamic dispatching rule based on self-organization for dispatching in a semiconductor manufacturing system, including S1: setting roles and parameters of self-organization units, and defining key nodes in a production environment; S2: constructing a negotiation mechanism between the self-organization units, and designing a decision-making and dispatching subject ESOU; S3: according to a decision instruction of the ESOU, designing a LSOU allocation dispatching unit for distinguishing single-batch processing and multi-batch processing; and S4: designing a dispatching mechanism based on the self-organization units to implement dynamic semiconductor dispatching. The dynamic dispatching method includes three aspects: role definitions of self-organization units, a negotiation mechanism between the self-organization units and a decision-making method thereof.

Abstract: An optimization method and system of matching a product experiencing activity with participants are disclosed. The method comprises the following steps: storing, in a memory, personal information of the applicants collected by conducting an investigation with questionnaires; clustering the personal information of the applicants to form a plurality of characteristic sample groups; evaluating a weight value of each of the applicants in each of the plurality of characteristic sample groups to produce a representative for each of the plurality of characteristic sample groups in accordance with the weight values; selecting a plurality of candidates to participate the experiencing activity in coordination with the characteristic sample groups and the representative according to an activity restriction of the experiencing activity; and notifying the candidates to participate the experiencing activity.