Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Abstract: An image processing method for a game loop of a game, wherein the game loop comprises a game rendering module and a MEMC module, and is executed by more than one processing unit to generate an output image to display. The image processing method includes rendering, by the game rendering module, a scene of the game to obtain a first image; rendering, by the game rendering module, a UI to obtain a second image; applying, by the MEMC module, MEMC to the first image to generate an interpolated first image; and blending, by the MEMC module, the second image and the interpolated first image into the output image.

Abstract: A stable frame rate is maintained by a system that includes a graphics processing unit (GPU). The system also includes memory to store frames rendered by the GPU, and a display to display the frames rendered by the GPU. In response to a negative indication with respect to the GPU maintaining a frame rate at an operating frequency, the GPU is operative to reduce frame quality of subsequent frames while maintaining the operating frequency.

Abstract: A stable frame rate is maintained by a system that includes a graphics processing unit (GPU). The system also includes memory to store frames rendered by the GPU, and a display to display the frames rendered by the GPU. In response to a negative indication with respect to the GPU maintaining a frame rate at an operating frequency, the GPU is operative to reduce frame quality of subsequent frames while maintaining the operating frequency.

Abstract: A board game in which players attempt to become President of the United States by accumulating the required amount of electoral votes. Each player has a first game piece to be used in one or more "non-special" sections and a second game piece to be used in a single "special" section. Within the non-special sections are space indicators which direct the one piece to various areas exclusively within the non-special section or sections. A few of the space indicators within the non-special sections indicate when the second playing piece is to be used exclusively within the special section. Within the special section are also space indicators which indicate various moves to be taken by the first playing piece positioned in the non-special sections. Also within the special section are space indicators which are for the accumulation of electoral votes or the accumulation of monetary value chips.