Abstract: The present disclosure relates to an innovative leather and a manufacturing method thereof. The innovative leather includes a TPU substrate, a TPU adhering layer, and a TPU surface layer. The TPU adhering layer is disposed on the TPU substrate. The TPU surface layer is disposed on the TPU adhering layer. All materials of the innovative leather of the present disclosure are the same TPU materials, thus the innovative leather of the present disclosure can be recycled after the innovative leather of the present disclosure is used. The innovative leather of the present disclosure has recycling benefit.

Abstract: A thin film transistor includes a bottom gate, a semiconductor layer, a top gate, a first auxiliary conductive pattern, a source, and a drain. The semiconductor layer includes a first semiconductor region, a second semiconductor region, a first heavily doped region, a second heavily doped region, a third heavily doped region, a first lightly doped region, a second lightly doped region, and a third lightly doped region. The first heavily doped region and the second heavily doped region are respectively located on two sides of the first semiconductor region. Two ends of the second semiconductor region are directly connected to the third heavily doped region and the third lightly doped region, respectively. The top gate is electrically connected to the bottom gate. The source and the drain are respectively electrically connected to the third heavily doped region and the second heavily doped region of the semiconductor layer.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Abstract: A semiconductor device includes a substrate, a bottom electrode, a ferroelectric layer, a noble metal electrode, and a non-noble metal electrode. The bottom electrode is over the substrate. The ferroelectric layer is over the bottom electrode. The noble metal electrode is over the ferroelectric layer. The non-noble metal electrode is over the noble metal electrode.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random access memory (FeRAM) device is over the substrate between the select gate and the first source/drain region. A transistor device is disposed on an upper surface of the substrate. The substrate has a recessed surface that is below the upper surface of the substrate and that is laterally separated from the upper surface of the substrate by a boundary isolation structure extending into a trench within the upper surface of the substrate. The FeRAM device is arranged over the recessed surface.

Abstract: A wideband planar dipole antenna comprises a substrate and two antenna bodies. Metal conductor is printed on the single surface/double surfaces of the substrate to form the antenna bodies. With a dipole antenna architecture, the antenna bodies are manufactured as loop structures similar to concentric circles. The loop structures can be of rectangular or circular shapes. Loops of metal conductors with different lengths resonate to obtain similar but different frequencies. Each path of every antenna body can be finally connected with a metal conductor sheet capable of changing to any shape. Every path can interfere with adjacent paths to achieve the wideband effect. An asymmetric mechanism can be added in one of the antenna bodies. Besides letting the antenna have the resonance effect of the symmetric part, the loop path at the signal source can also be increased to enhance the receiving performance of the antenna.

Abstract: A wideband planar dipole antenna comprises a substrate and two antenna bodies. Metal conductor is printed on the single surface/double surfaces of the substrate to form the antenna bodies. With a dipole antenna architecture, the antenna bodies are manufactured as loop structures similar to concentric circles. The loop structures can be of rectangular or circular shapes. Loops of metal conductors with different lengths resonate to obtain similar but different frequencies. Each path of every antenna body can be finally connected with a metal conductor sheet capable of changing to any shape. Every path can interfere with adjacent paths to achieve the wideband effect. An asymmetric mechanism can be added in one of the antenna bodies. Besides letting the antenna have the resonance effect of the symmetric part, the loop path at the signal source can also be increased to enhance the receiving performance of the antenna.

Abstract: A method of reducing the photoelectric device leakage current caused by residual metal ions in conjugated polymer. A chelating agent is added to a conjugated polymer material, thereby the conductivity and mobility of metal ions under an electric field are reduced due to the chelation of metal ions by the chelating agent; therefore, the leakage current is reduced and the stability of devices is improved. Furthermore, the activity of metal ions is reduced after the metal ions are chelated by the chelating agent, improving the stability of the material and the devices. A conjugated polymer composition is also provided.

Abstract: A method of reducing the photoelectric device leakage current caused by residual metal ions in conjugated polymer. A chelating agent is added to a conjugated polymer material, thereby the conductivity and mobility of metal ions under an electric field are reduced due to the chelation of metal ions by the chelating agent; therefore, the leakage current is reduced and the stability of devices is improved. Furthermore, the activity of metal ions is reduced after the metal ions are chelated by the chelating agent, improving the stability of the material and the devices. A conjugated polymer composition is also provided.