Abstract: A thin film transistor includes a bottom gate, a semiconductor layer, a top gate, a first auxiliary conductive pattern, a source, and a drain. The semiconductor layer includes a first semiconductor region, a second semiconductor region, a first heavily doped region, a second heavily doped region, a third heavily doped region, a first lightly doped region, a second lightly doped region, and a third lightly doped region. The first heavily doped region and the second heavily doped region are respectively located on two sides of the first semiconductor region. Two ends of the second semiconductor region are directly connected to the third heavily doped region and the third lightly doped region, respectively. The top gate is electrically connected to the bottom gate. The source and the drain are respectively electrically connected to the third heavily doped region and the second heavily doped region of the semiconductor layer.

Abstract: A method of forming low-k material is provided. The method includes providing a plurality of core-shell particles. The core of the core-shell particles has a first ceramic with a low melting point. The shell of the core-shell particles has a second ceramic with a low melting point and a low dielectric constant. The core-shell particles are sintered and molded to form a low-k material. The shell of the core-shell particles is connected to form a network structure of a microcrystal phase.

Abstract: A bonded assembly includes an interposer; a semiconductor die that is attached to the interposer and including a planar horizontal bottom surface and a contoured sidewall; a high bandwidth memory (HBM) die that is attached to the interposer; and a dielectric material portion contacting the semiconductor die and the interposer. The contoured sidewall includes a vertical sidewall segment and a non-horizontal, non-vertical surface segment that is adjoined to a bottom edge of the vertical sidewall segment and is adjoined to an edge of the planar horizontal bottom surface of the semiconductor die. The vertical sidewall segment and the non-horizontal, non-vertical surface segment are in contact with the dielectric material portion. The contoured sidewall may provide a variable lateral spacing from the HBM die to reduce local stress in a portion of the HBM die that is proximal to the interposer.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.

Abstract: A method of forming a FinFET is disclosed. The method includes depositing a conductive material across each of a number of adjacent fins, depositing a sacrificial mask over the conductive material, patterning the conductive material with the sacrificial mask to form a plurality of conductive material segments, depositing a sacrificial layer over the sacrificial mask, and patterning the sacrificial layer, where a portion of the patterned sacrificial layer remains over the sacrificial mask, where a portion of the sacrificial mask is exposed, and where the exposed portion of the sacrificial mask extends across each of the adjacent fins. The method also includes removing the portion of the sacrificial layer over the sacrificial mask, after removing the portion of the sacrificial layer over the sacrificial mask, removing the sacrificial mask, epitaxially growing a plurality of source/drain regions from the semiconductor substrate, and electrically connecting the source/drain regions to other devices.

Abstract: A method includes bonding a first device die to a second device die through face-to-face bonding, wherein the second device die is in a device wafer, forming a gap-filling region to encircle the first device die, performing a backside-grinding process on the device wafer to reveal a through-via in the second device die, and forming a redistribution structure on the backside of the device wafer. The redistribution structure is electrically connected to the first device die through the through-via in the second device die. A supporting substrate is bonded to the first device die.

Abstract: A pixel array substrate, including multiple pixel structures, multiple data lines, multiple scan line groups, multiple transfer line groups, multiple connection terminal groups, and multiple bridge line groups, is provided. The multiple data lines are electrically connected to the multiple pixel structures and arranged in a first direction. Each scan line group includes multiple scan lines arranged in a second direction. The multiple scan lines of the multiple scan line groups are electrically connected to the multiple pixel structures. Each transfer line group includes multiple transfer lines arranged in the first direction. The multiple transfer lines of each transfer line group are electrically connected to the multiple scan lines of a corresponding scan line group. The bridge line groups are structurally separated. Each bridge line group is electrically connected to a corresponding transfer line group and a corresponding connection terminal group.

Abstract: The present invention provides a light emitting panel, which includes: a substrate, at least one light emitting element disposed on the substrate, and a reflective structure layer. The reflective structure layer includes a plurality of first microstructure units disposed on the substrate and distributed around the at least one light emitting element, and a plurality of second microstructure units disposed on and overlapping the first microstructure units. A spacing between adjacent first microstructure units among the first microstructure units is less than a spacing between adjacent second microstructure units among the second microstructure units.

Abstract: A circuit substrate includes a substrate, an active device, a first signal line, a second signal line, a shielding electrode, a data line, a pixel electrode, and a common electrode. The first signal line is electrically connected to the active device, and includes a main portion and a connection portion connected to the main portion. The main portion extends along a first direction. The second signal line extends along a second direction. The second signal line is electrically connected to the connection portion. The shielding electrode overlaps the connection portion in a normal direction of the substrate. The shielding electrode and the second signal line belong to a same conductive layer. The data line is electrically connected to the active device. The common electrode is electrically connected to the shielding electrode.

Abstract: A pixel array substrate, including multiple pixel structures, multiple data lines, multiple scan line groups, multiple transfer line groups, multiple connection terminal groups, and multiple bridge line groups, is provided. The multiple data lines are electrically connected to the multiple pixel structures and arranged in a first direction. Each scan line group includes multiple scan lines arranged in a second direction. The multiple scan lines of the multiple scan line groups are electrically connected to the multiple pixel structures. Each transfer line group includes multiple transfer lines arranged in the first direction. The multiple transfer lines of each transfer line group are electrically connected to the multiple scan lines of a corresponding scan line group. The bridge line groups are structurally separated. Each bridge line group is electrically connected to a corresponding transfer line group and a corresponding connection terminal group.

Abstract: A photosensitive element and a manufacturing method thereof are provided. The manufacturing method of the photosensitive element includes successively depositing a second conductive layer, a photosensitive material layer, and a first top electrode material layer on a substrate; forming a first patterned photoresist layer on the first top electrode material layer; patterning the first top electrode material layer by using the first patterned photoresist layer as a mask to form a first top electrode; removing the first patterned photoresist layer; patterning the photosensitive material layer by using the first top electrode as a mask to form a photosensitive layer; forming an insulation layer having an opening on the first top electrode; and forming a second top electrode on the insulation layer, and the second top electrode is electrically connected to the first top electrode via the opening.

Abstract: A display panel includes a substrate, at least one first transistor, and at least one second transistor. The substrate includes at least one reflective region and at least one transmissible region. The first transistor is configured on the substrate and located on the corresponding reflective region. Each of the first transistors includes a first active layer. The second transistor is configured on the substrate and located on the corresponding transmissible region. Each of the second transistors includes a second active layer. A material of the first active layer is different from a material of the second active layer.

Abstract: An active device substrate and a manufacturing method thereof are provided. The active device substrate includes a substrate, first and second scan lines, a data line, first and second active devices and first and second pixel electrodes. The first active device includes a first semiconductor channel layer, a first gate, a first source and a first drain. The first gate is electrically connected to the first scan line. The first pixel electrode is electrically connected to the first drain. The second active device includes a second semiconductor channel layer, a second gate and a second drain. The first semiconductor channel layer is connected to a source region of the second semiconductor channel layer. The first semiconductor channel layer and the second semiconductor channel layer belong to same layer. The second gate is electrically connected to the second scan line. The second pixel electrode is electrically connected to the second drain.

Abstract: An opposite substrate including a substrate, first light-shielding patterns, second light-shielding patterns, a planarization layer and support members is provided. The support members are located in primary support regions and secondary support regions of the opposite substrate. The first light-shielding patterns respectively extend along a first direction, and a material of the first light-shielding patterns includes an organic material. The second light-shielding patterns respectively extend along a second direction, and a material of the second light-shielding patterns includes metal. The first light-shielding patterns and the second light-shielding patterns are respectively located at opposite sides of the planarization layer. Alternatively, the first light-shielding patterns and the second light-shielding patterns are located at the same side of the planarization layer, and the planarization layer has openings respectively overlapped with the support members located in the secondary support regions.

Abstract: A pixel array substrate including a substrate, an active device, a planarization layer, a first conductive layer, a first insulation layer and a second conductive layer is provided. The active device is disposed on the substrate. The planarization layer covers the active device and has a first opening. The first conductive layer is disposed on the planarization layer and is electrically connected with a first end of the active device. The first insulation layer is disposed on the first conductive layer. The second conductive layer is disposed on the first insulation layer. The first conductive layer and the second conductive layer cover a side surface of the first opening of the planarization layer.

Abstract: A pixel array substrate including a substrate, an active device, a planarization layer, a first conductive layer, a first insulation layer and a second conductive layer is provided. The active device is disposed on the substrate. The planarization layer covers the active device and has a first opening. The first conductive layer is disposed on the planarization layer and is electrically connected with a first end of the active device. The first insulation layer is disposed on the first conductive layer. The second conductive layer is disposed on the first insulation layer. The first conductive layer and the second conductive layer cover a side surface of the first opening of the planarization layer.

Abstract: An active device substrate and a manufacturing method thereof are provided. The active device substrate includes a substrate, first and second scan lines, a data line, first and second active devices and first and second pixel electrodes. The first active device includes a first semiconductor channel layer, a first gate, a first source and a first drain. The first gate is electrically connected to the first scan line. The first pixel electrode is electrically connected to the first drain. The second active device includes a second semiconductor channel layer, a second gate and a second drain. The first semiconductor channel layer is connected to a source region of the second semiconductor channel layer. The first semiconductor channel layer and the second semiconductor channel layer belong to same layer. The second gate is electrically connected to the second scan line. The second pixel electrode is electrically connected to the second drain.

Abstract: A photosensitive element and a manufacturing method thereof are provided. The manufacturing method of the photosensitive element includes successively depositing a second conductive layer, a photosensitive material layer, and a first top electrode material layer on a substrate; forming a first patterned photoresist layer on the first top electrode material layer; patterning the first top electrode material layer by using the first patterned photoresist layer as a mask to form a first top electrode; removing the first patterned photoresist layer; patterning the photosensitive material layer by using the first top electrode as a mask to form a photosensitive layer; forming an insulation layer having an opening on the first top electrode; and forming a second top electrode on the insulation layer, and the second top electrode is electrically connected to the first top electrode via the opening.

Abstract: A display panel includes a substrate, at least one first transistor, and at least one second transistor. The substrate includes at least one reflective region and at least one transmissible region. The first transistor is configured on the substrate and located on the corresponding reflective region. Each of the first transistors includes a first active layer. The second transistor is configured on the substrate and located on the corresponding transmissible region. Each of the second transistors includes a second active layer. A material of the first active layer is different from a material of the second active layer.