Abstract: A method, includes: in a strap cell disposed between a memory cell and a logic cell, arranging a first gate across an active region; arranging a second gate next to and in parallel with the first gate and at an end of the active region; and when at least one conductive segment has a first length, arranging the at least one conductive segment across the first gate, the second gate, and no dummy gate in the strap cell. A semiconductor device is also disclosed herein.

Abstract: A memory device is disclosed that includes memory cell, e strap cell, conductive segment, and logic cell. The strap cell is arranged abutting the memory cell. The strap cell includes an active region, a first gate, and a second gate. The first gate is arranged across the active region. The second gate is arranged across the active region and disposed at the end of active region. The conductive segment is disposed over the first gate and the second gate. The strap cell is disposed between the memory cell and the logic cell, and the logic cell includes a third gate. The conductive segment is spaced apart from the third gate, and the length of the conductive segment is smaller than five times of a gate pitch between the first gate and the second gate.

Abstract: A data storage device in a two-layer control structure is provided. A control unit of the data storage device has a command processor and a first non-volatile memory (NVM) controller. The command processor is operative to communicate with a host. The first non-volatile memory (NVM) controller operates a first NVM of the data storage device. Earlier than the command processor operates according to a ROM image corresponding to the command processor, the first NVM controller operates according to a ROM image corresponding to the first NVM controller to access the first NVM to get a firmware image for the command processor and loads the command processor with the firmware image.

Abstract: A data storage device with fault-tolerant design. The data storage device has a RAID (Redundant Array of Independent Disks) engine that generates RAID checking code for user data requested in a write command. The user data is programmed to a non-volatile memory according to a target physical address indicated in the write command. The RAID checking code is programmed to the non-volatile memory according to a reserved physical address. The user data and the RAID checking code are programmed to a stripe of pages within a stripe of blocks.

Abstract: A memory device is disclosed that includes memory cell, e strap cell, conductive segment, and logic cell. The strap cell is arranged abutting the memory cell. The strap cell includes an active region, a first gate, and a second gate. The first gate is arranged across the active region. The second gate is arranged across the active region and disposed at the end of active region. The conductive segment is disposed over the first gate and the second gate. The strap cell is disposed between the memory cell and the logic cell, and the logic cell includes a third gate. The conductive segment is spaced apart from the third gate, and the length of the conductive segment is smaller than five times of a gate pitch between the first gate and the second gate.

Abstract: A data storage device with fault-tolerant design. The data storage device has a RAID (Redundant Array of Independent Disks) engine that generates RAID checking code for user data requested in a write command. The user data is programmed to a non-volatile memory according to a target physical address indicated in the write command. The RAID checking code is programmed to the non-volatile memory according to a reserved physical address. The user data and the RAID checking code are programmed to a stripe of pages within a stripe of blocks.

Abstract: A data storage device in a two-layer control structure is provided. A control unit of the data storage device has a command processor and a first non-volatile memory (NVM) controller. The command processor is operative to communicate with a host. The first non-volatile memory (NVM) controller operates a first NVM of the data storage device. Earlier than the command processor operates according to a ROM image corresponding to the command processor, the first NVM controller operates according to a ROM image corresponding to the first NVM controller to access the first NVM to get a firmware image for the command processor and loads the command processor with the firmware image.

Abstract: A circuit includes a fuse cell, a sense circuit and an output control circuit. The fuse cell includes an electrical fuse. The sense circuit is electrically coupled to the fuse cell and configured for generating a sense signal indicative of a programmed condition of the electrical fuse, at an output of the sense circuit. The output control circuit is electrically coupled to the output of the sense circuit, and the output control circuit is configured for latching the sense signal indicative of the electrical fuse having been programmed, during a read operation of the fuse cell.

Abstract: A circuit includes a fuse cell, a sense circuit and an output control circuit. The fuse cell includes an electrical fuse. The sense circuit is electrically coupled to the fuse cell and configured for generating a sense signal indicative of a programmed condition of the electrical fuse, at an output of the sense circuit. The output control circuit is electrically coupled to the output of the sense circuit, and the output control circuit is configured for latching the sense signal indicative of the electrical fuse having been programmed, during a read operation of the fuse cell.

Abstract: A method for forming a porous material is to mix a porous first basic material with a sacrificial material compatible with the first basic material to let the sacrificial material permeate into the pores of the first basic material to form a first finished product. Subsequently, the first finished product is mixed with a second basic material and heated over the vaporization temperature of the sacrificial material to let the ingredients of the second basic material change and increase viscous force and impossible to enter the pores of the first basic material. Simultaneously, the sacrificial material is heated and vaporized to exhaust out of the pores of the first basic material, disabling the second basic material to permeate into the pores of the first basic material and thus forming a second finished product for reserving the ingredients in the pores of the first basic material.

Abstract: The present invention provides a dielectric constant adjustable resin composition, a pre-preg, and a copper clad laminate utilizing. The dielectric constant adjustable resin composition includes a curable polyphenylene ether (PPE) resin, a curing agent, a free radical initiator, and a dielectric ceramic powder with a particle size of 0.1 to 2 m um modified with a lipophilic modifier.

Abstract: PPE copolymers comprise three repeating units. The PPE copolymers are polymerized with 2,6-DMP, dialkenylamide or dialkenylamine phenol, and another phenol derivative. A resin composition having a low cross-linking temperature is also disclosed, which comprises the PPE copolymer and a free radical initiator.

Abstract: PPE copolymers comprise three repeating units. The PPE copolymers are polymerized with 2,6-DMP, dialkenylamide or dialkenylamine phenol, and another phenol derivative. A resin composition having a low cross-linking temperature is also disclosed, which comprises the PPE copolymer and a free radical initiator.

Abstract: A layered clay material is modified by ion exchange with (1) ZrOCl2 and (2) a silane surfactant. The modified clay material is heat-kneaded with epoxy oligomers to undergo polymerization, thus obtaining an epoxy/clay composite comprising the clay material uniformly dispersed in the epoxy resin matrix on a nano-scale. The epoxy/clay nanocomposite has excellent adhesion and less hygroscopicity, which makes it especially suitable as molding or packaging material for electronic devices.

Abstract: A semiconductor memory device having a parallel data test scheme is disclosed. The semiconductor memory includes an array that is partitioned into array portions with each array portion further divided into sub-arrays and banks. Each array portion providing data bits to a data compression circuit. The data compression circuit includes data compare sections and ripple sections. The data compare sections include data compare circuits that compare the data bits provided by each array portion and each provide a compare output to the ripple sections. The ripple sections are coupled together in series and provide global data compare outputs. A multiplexer selects between a data bit and the global data compare outputs to provide either a data output or a data comparison output to the output pin.

Abstract: A triazine compound having formula I or formula II: Wherein n is integer from 1 to 5; R1 is hydrogen, halogen, C1-C4 alkyl, or C1-C4 alkoxyl; and R2 is aliphatic amine, aliphatic alcohol, alicyclic amine or alicyclic alcohol, and an epoxy resin composition containing the triazine compound. The epoxy resin composition is suitable for the preparation of the structural substrate of printed circuit boards having low dielectric constant.

Abstract: An architecture for a high-capacity high-speed semiconductor memory device is disclosed. The semiconductor memory device includes memory cell arrays (406) having local word lines and bit lines. The memory cell arrays (406) are further arranged into array groups (402a-402d and 404a-404d). The local word lines (410a-410d) of the memory cell arrays of the same group are commonly connected to global word lines (408). The array groups (402a-402d and 404a-404d) provide data access paths to their respective memory cells by sets of input/output (I/O) lines (416a-416d and 420a-420d). The I/O line sets (416a-416d and 420a-420d) are coupled to data amplifiers by interarray multiplexers (MUXs) (422a-422d). The interarray MUXs (422a-422d) enable defective global word lines of one array group to be replaced by redundant global word lines of an adjacent array group.

Abstract: A circuit for reducing the transmission delay of the SDRAM by using a cascade-amplifying scheme. The circuit principally encompasses a memory array core for storing data, a main amplifier for initially amplifying the data, an MO-pair receiving amplifier for recognizing and amplifying the data, and an output neighborhood for outputting the data when the data convey a log data path. When the required data output from the memory array core is amplified by the main amplifier, the differential level of the required data will appear at both the far end and the near end of the data path. Therefore, the transmitted data at the far end can be amplified again as long as the differential level is sufficient.

Abstract: The present invention is related to an input device controller having a photo coupler generating an induced current in response to a received quantum of light and using multi-stage, e.g. three-stage, dynamic impedances as an impedance match to obtain better frequency response and accurate identification of light-pass/light-shield state of the photo coupler. It also related to an input device controller using a reference voltage supply circuit including a constant current generator and an equivalent circuit to avoid the bad effect on the cursor shift control caused by the variation of the reference voltage.