Abstract: A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.

Abstract: A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.

Abstract: A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed.

Abstract: An architecture, circuit and method for providing a high speed operation DRAM memory with reduced cell disturb. A DRAM global bit line select circuit couples a pair of local bit lines and the associated sense amplifier to the global bit lines using a circuit optimized for high speed operation. The select circuit and method also reduces or eliminates the bit line disturb effect of the prior art. The circuit and architecture of the DRAM incorporating the select circuit is particularly useful for embedding DRAM memory with other logic in an integrated circuit. For a read operation the select circuit discharges the appropriate global bit line directly to ground thus speeding the read cycles. For a write operation, a dedicated control line is used to couple write data to from the global bit lines to the selected local bit lines. Methods for operating the DRAM and the select circuits are disclosed.

Abstract: A system and a method is disclosed for allowing bandgap circuitry to function on a low supply voltage integrated circuit, and for using the reference voltage (Vbg) generated by the bandgap circuitry to enable a reference voltage to control system voltage. An illustrative embodiment comprises a charge pump to raise a supply voltage to a system voltage, and an open loop controller, which provides a first signal to activate the charge pump, enabling a bandgap circuit, which outputs a bandgap voltage reference. Further, the system comprises a closed loop controller, which regulates the system voltage by comparing the system voltage to the bandgap reference voltage. Upon the system voltage falling below a target voltage, the closed loop controller provides a second signal to activate the charge pump. Additionally the system comprises a switch controller, which selects the closed loop controller upon sensing the bandgap circuit is active.

Abstract: A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.

Abstract: A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and a second global bit line coupled to the first and the second local bit lines, respectively. The method further includes starting an equalization to equalize voltages on the first and the second local bit lines; stopping the equalization; and after the step of starting the equalization and before the step of stopping the equalization, writing values from the first and the second global bit lines to the first and the second local bit lines.

Abstract: A system and a method is disclosed for allowing bandgap circuitry to function on a low supply voltage integrated circuit, and for using the reference voltage (Vbg) generated by the bandgap circuitry to enable a reference voltage to control system voltage. An illustrative embodiment comprises a charge pump to raise a supply voltage to a system voltage, and an open loop controller, which provides a first signal to activate the charge pump, enabling a bandgap circuit, which outputs a bandgap voltage reference. Further, the system comprises a closed loop controller, which regulates the system voltage by comparing the system voltage to the bandgap reference voltage. Upon the system voltage falling below a target voltage, the closed loop controller provides a second signal to activate the charge pump. Additionally the system comprises a switch controller, which selects the closed loop controller upon sensing the bandgap circuit is active.

Abstract: An architecture, circuit and method for providing a high speed operation DRAM memory with reduced cell disturb. A DRAM global bit line select circuit couples a pair of local bit lines and the associated sense amplifier to the global bit lines using a circuit optimized for high speed operation. The select circuit and method also reduces or eliminates the bit line disturb effect of the prior art. The circuit and architecture of the DRAM incorporating the select circuit is particularly useful for embedding DRAM memory with other logic in an integrated circuit. For a read operation the select circuit discharges the appropriate global bit line directly to ground thus speeding the read cycles. For a write operation, a dedicated control line is used to couple write data to from the global bit lines to the selected local bit lines. Methods for operating the DRAM and the select circuits are disclosed.