Abstract: A serial digital signal transmission apparatus can transmit HDTV digital serial signals with little jitter while utilizing the SRTS method. In the apparatus, parallel clocks are counted by an N counter to be supplied to the latch circuit, which latches the output count of a p-bit counter, RTSs are supplied from the latch circuit, as the result of comparison gated by a gate circuit is supplied to a PLL circuit and multiplied by N, parallel clocks of 74.25 MHz or 74.25/1.001 MHz, which are inputs to the N counter are regenerated (N is 8, 15 or 16), and transmitted data undergo parallel-to-serial conversion by a PS converter with these parallel clocks.

Abstract: A storage circuit defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing the first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit divides the first header bits by a generator polynomial to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.

Abstract: A storage circuit defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing the first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit divides the first header bits by a generator polynomial to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.

Abstract: A serial digital signal transmission apparatus can transmit HDTV digital serial signals with little jitter while utilizing the SRTS method. In the apparatus, parallel clocks are counted by an N counter to be supplied to the latch circuit, which latches the output count of a p-bit counter, RTSs are supplied from the latch circuit, as the result of comparison gated by a gate circuit is supplied to a PLL circuit and multiplied by N, parallel clocks of 74.25 MHz or {fraction (74.25/1.001)} MHz, which are inputs to the N counter are regenerated (N is 8, 15 or 16), and transmitted data undergo parallel-to-serial conversion by a PS converter with these parallel clocks.

Abstract: In a clock signal reproducing circuit in a pulse stuffed synchronizing system, a destuffing circuit removes stuff pulses and unnecessary bits from a higher order group signal to output a lower order group signal, and outputs stuff data indicating existence or non-existence of positive stuff or negative stuff in the higher order group signal. A storage circuit stores the lower order group signal outputted from the destuffing circuit. A stuff rate determining circuit determines a stuff rate from a difference between the number of positive stuffs and the number of negative stuffs to a stuffing possible period of the higher order group signal based on the stuff data outputted from the destuffing circuit. A variable frequency divider frequency-divides a clock signal of the higher order group signal based on the control signal outputted from the control circuit.

Abstract: A loose source routing method is provided to transfer an IP packet from a transmission source gateway to a transfer destination gateway by way of ATM nodes, which are freely designated. At the transmission source gateway, the IP packet given from a user LAN is dissolved into ATM cells containing a BOM cell whose destination address designates the transfer destination gateway. In addition, at least one pseudo BOM cell whose destination address designates an ATM node in the ATM network is added and is located at a top place of a cell stream constructed by the dissolved ATM cells. Thus, the cell stream is transferred from the transmission source gateway to the designated ATM node in accordance with the destination address of the pseudo BOM cell. The designated ATM node discards the pseudo BOM cell so that the original BOM cell is now located at the top place of the cell stream.

Abstract: A storage circuit defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing signal first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit divides the first header bits by a generator polynomial to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.

Abstract: An SRTS receiver for reproducing a user clock by applying combined pulses to phase synchronous oscillation unit, the SRTS receiver comprises a RTS information receiving unit for generating pulses in N-clock cycle of the user clock on average according to the received RTS information, an interpolation pulse generating unit for generating interpolation pulse signals to be inserted in the pulses generated by the RTS information receiving unit, and a pulse combining unit for combining the interpolation pulses supplied from the interpolation pulse generating unit and the pulses generated by the RTS information receiving unit and supplying the same.

Abstract: A numerically controlled oscillator including an RTS value producing circuit which produces a series of residual time stamp (RTS) values indicative of a relation between the setting value and an actual oscillation frequency. A pulse train generator generates a pulse train in a period corresponding to the produced series of RTS values and a phase synchronous oscillator oscillates at a frequency in synchronism with the pulse train output from the pulse train generator. Preferably, the pulse train generated by the pulse train generator is supplied to the RTS value producing circuit as a signal indicative of the actual oscillation frequency.

Abstract: In an RTS generator used in an ATM network where a network reference clock is continuously counted to produce the lower four bits of a counted number, which are, in turn, latched in response to a latching pulse signal produced by frequency dividing a CBR clock by N=3008, the latched number providing the RTS, the lower four bits are formed on the base of the Gray code so as to avoid latching of abnormal number even in racing condition between the change of the counted number and a rising of the latching pulse.

Abstract: In a frame aligner for frame aligning an input time-division multiplexed (TDM) signal to an output frame synchronous signal, an input frame signal of the TDM signal is separated into a transport overhead carrying an input frame synchronous signal and a message pointer and a subframe carrying data signal. A fresh overhead having a fresh pointer is made corresponding to a phase difference between said input and said output frame synchronous signals and said subframe is sequentially written into and read from a buffer memory. The fresh overhead and the subframe read are multiplexed to form an output TDM frame signal which is synchronized with the output frame synchronous signal. The buffer memory is permitted to have a reduced memory capacity storable a number of channel signals equal to that of time slots carrying the overhead.

Abstract: A stuff synchronization circuit includes a memory, a phase comparison D flip-flop, a stuff judgment flip-flop, and a control section including selectors and an encoder. In the memory, writing and reading are performed at different timings. The phase comparison D flip-flop detects a phase difference between a write timing for a specific bit included in data input to the memory and a read timing for the specific bit. The stuff judgment D flip-flop judges an insertion timing of stuff pulses on the basis of the detected phase difference. The control section keeps a time interval between a time at which the phase difference is detected by the phase comparison D flip-flop and a time at which the insertion timing of stuff pulses is judged by the stuff judgment D flip-flop constant.