Patents by Inventor Kuriyama MASAO

Kuriyama MASAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PAGE BUFFER CIRCUIT WITH BIT LINE SELECT TRANSISTOR
    Publication number: 20230154545
    Abstract: Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bit line and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bit line can include a first bit line segment coupled to the first memory string group and a second bit line segment coupled to the second memory string group. The buffer can be coupled to the memory array by the bit line. The memory array and the buffer can be included in separate first and second dies, respectively, and the first die can be bonded to the second die.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 18, 2023
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Teng CHEN, Yan WANG, Jing WEI, Yang ZHANG, Kuriyama MASAO
  • Page buffer circuit with bit line select transistor
    Patent number: 11581045
    Abstract: Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bitline and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bitline can include a first bitline segment coupled to the first memory string group and a second bitline segment coupled to the second memory string group. The first bitline segment can be disposed between the first memory string group and the buffer and be connected to the buffer through a first conduction path. The second bitline segment can be disposed between the second memory string group and the buffer and be connected to the buffer through a second conduction path.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: February 14, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Teng Chen, Yan Wang, Jing Wei, Yang Zhang, Kuriyama Masao
  • PAGE BUFFER CIRCUIT WITH BIT LINE SELECT TRANSISTOR
    Publication number: 20220189559
    Abstract: Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bitline and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bitline can include a first bitline segment coupled to the first memory string group and a second bitline segment coupled to the second memory string group. The first bitline segment can be disposed between the first memory string group and the buffer and be connected to the buffer through a first conduction path. The second bitline segment can be disposed between the second memory string group and the buffer and be connected to the buffer through a second conduction path.
    Type: Application
    Filed: March 3, 2021
    Publication date: June 16, 2022
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Teng CHEN, Yan WANG, Jing WEI, Yang ZHANG, Kuriyama MASAO