Abstract: A system, processor, programming product and/or method for assigning instructions to destination register file blocks, and/or routing instructions, includes: providing a processing pipeline having two or more execution units configured to process instructions; providing a register file having register file entries configured to hold data, where the register file is subdivided into a plurality of register blocks and each register block has two or more register file entries; calculating a utilization rate for one or more register blocks; and assigning and/or routing an instruction to write its results to a register block based upon the utilization rate for that register block. Preferably the execution unit is configured to write its results to a single specific destination (rename) register block.

Abstract: A method of instruction dispatch routing comprises receiving an instruction for dispatch to one of a plurality of issue queues; determining a priority status of the instruction; selecting a rotation order based on the priority status, wherein a first rotation order is associated with priority instructions and a second rotation order, different from the first rotation order, is associated with non-priority instructions; selecting an issue queue of the plurality of issue queues based on the selected rotation order; and dispatching the instruction to the selected issue queue.

Abstract: In at least one embodiment, a processor includes architected and non-architected register files for buffering operands. The processor additionally includes an instruction fetch unit that fetches instructions to be executed and at least one execution unit. The at least one execution unit is configured to execute a first class of instructions that access operands in the architected register file and a second class of instructions that access operands in the non-architected register file. The processor also includes a mapper circuit that assigns physical registers to the instructions for buffering of operands. The processor additionally includes a dispatch circuit configured, based on detection of an instruction in one of the first and second classes of instructions for which correct operands do not reside in a respective one of the architected and non-architected register files, to automatically initiate transfer of operands between the architected and non-architected register files.

Abstract: A method of instruction dispatch routing comprises receiving an instruction for dispatch to one of a plurality of issue queues; determining a priority status of the instruction; selecting a rotation order based on the priority status, wherein a first rotation order is associated with priority instructions and a second rotation order, different from the first rotation order, is associated with non-priority instructions; selecting an issue queue of the plurality of issue queues based on the selected rotation order; and dispatching the instruction to the selected issue queue.

Abstract: In at least one embodiment, a processor includes architected register file and non-architected register files for buffering operands. The processor additionally includes an instruction fetch unit that fetches instructions to be executed and at least one execution unit. The at least one execution unit is configured to execute a first class of instructions that access operands in the architected register file and a second class of instructions that access operands in the non-architected register file. The processor also includes a mapper circuit that assigns physical registers to the instructions for buffering of operands. The processor additionally includes a dispatch circuit configured, based on detection of an instruction in one of the first and second classes of instructions for which correct operands do not reside in a respective one of the architected and non-architected register files, to automatically initiate transfer of operands between the architected and non-architected register files.

Abstract: In an approach to dynamic redistribution of register files, whether a redistribution of register files is necessary is determined. Responsive to determining that the redistribution of register files is necessary, one or more register file transfers that have not yet completed are flushed. One or more register file write locations are allocated for each architected register based on a register free list. Source data is read from each architected register. The source data is written to the one or more register file write locations.

Abstract: Parallel dispatching of multi-operation instructions in a multi-slice computer processor, including: determining whether an instruction must be broken into a plurality of smaller operations; marking each of the smaller operations as instructions to be dispatched in parallel; determining whether each of the operations can be dispatched to distinct instruction issue queues during a same clock cycle; and responsive to determining that each of the operations can be dispatched to distinct instruction issue queues during the same clock cycle, dispatching each of the operations to distinct instruction issue queues during the same clock cycle.

Abstract: An approach is disclosed that that in one or more embodiments includes receiving an indicator to issue an out-of-order instruction or a type of out-of-order instruction in-order; receiving a first instruction; determining whether the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction; writing, in response to determining that the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction, an instruction identifier and a dependent instruction opcode into a first queue and an issue queue of the processor; receiving at least one subsequent instruction; determining whether an instruction opcode of the subsequent instructions matches the dependent instruction opcode of the first instruction; and writing, in response to determining the instruction opcode of the subsequent instruction matches the dependent instruction opcode of the instruction, a dependent instruction identifier for the subsequent instruc

Abstract: A computer system, processor, and method for processing information is disclosed that includes a Dispatch Unit for dispatching instructions; an Issue Queue for receiving instructions dispatched from the Dispatch Unit; and a queue for receiving instructions issued from the Issue Queue, the queue having a plurality of entry locations for storing data. In an embodiment instructions are dispatched with a virtual indicator, and the virtual indicator is set to a first mode for instructions dispatched where an entry location is available, and to a second mode where an entry location is not available, in the queue to receive the dispatched instruction. In addition to virtual tagging dispatched instructions, a system, processor, and method are disclosed for regional partitioning of queues, region based deallocation of queue entries, and circular thread based assignment of queue entries.

Abstract: Supplemental instruction dispatch may be used in some instances in a parallel slice processor to dispatch additional instructions, referred to as supplemental instructions, to supplemental instruction ports of execution slices and using primary instruction ports of one or more execution slices to supply one or more source operands for such supplemental instructions. In addition, in some instances, in lieu of or in addition to supplemental instruction dispatch, selective slice partitioning may be used to selectively partition groups of execution slices in a parallel slice processor based upon a threading mode within which such execution slices are executing.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and an instruction sequencing unit. Operation of such a multi-slice processor includes: receiving, at the instruction sequencing unit, a load instruction indicating load address data and a load data length; determining a previous store instruction in an issue queue such that store address data for the previous store instruction corresponds to the load address data, wherein the previous store instruction corresponds to a store data length; and generating, in dependence upon the store data length matching the load data length, an indication in the issue queue that indicates a dependency between the load instruction and the previous store instruction.

Abstract: An approach is disclosed that in one or more embodiments includes receiving an indicator to issue an out-of-order instruction or a type of out-of-order instruction in-order; receiving a first instruction; determining whether the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction; writing, in response to determining that the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction, an instruction identifier and a dependent instruction opcode into a first queue and an issue queue of the processor; receiving at least one subsequent instruction; determining whether an instruction opcode of the subsequent instructions matches the dependent instruction opcode of the first instruction; and writing, in response to determining the instruction opcode of the subsequent instruction matches the dependent instruction opcode of the instruction, a dependent instruction identifier for the subsequent instruction

Abstract: A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.

Abstract: A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.

Abstract: Parallel dispatching of multi-operation instructions in a multi-slice computer processor, including: determining whether an instruction must be broken into a plurality of smaller operations; marking each of the smaller operations as instructions to be dispatched in parallel; determining whether each of the operations can be dispatched to distinct instruction issue queues during a same clock cycle; and responsive to determining that each of the operations can be dispatched to distinct instruction issue queues during the same clock cycle, dispatching each of the operations to distinct instruction issue queues during the same clock cycle.

Abstract: A computer system, processor, and method for processing information is disclosed that includes a Dispatch Unit for dispatching instructions; an Issue Queue for receiving instructions dispatched from the Dispatch Unit; and a queue for receiving instructions issued from the Issue Queue, the queue having a plurality of entry locations for storing data. In an embodiment instructions are dispatched with a virtual indicator, and the virtual indicator is set to a first mode for instructions dispatched where an entry location is available, and to a second mode where an entry location is not available, in the queue to receive the dispatched instruction. In addition to virtual tagging dispatched instructions, a system, processor, and method are disclosed for regional partitioning of queues, region based deallocation of queue entries, and circular thread based assignment of queue entries.

Abstract: Parallel dispatching of multi-operation instructions in a multi-slice computer processor, including: determining whether an instruction must be broken into a plurality of smaller operations; marking each of the smaller operations as instructions to be dispatched in parallel; determining whether each of the operations can be dispatched to distinct instruction issue queues during a same clock cycle; and responsive to determining that each of the operations can be dispatched to distinct instruction issue queues during the same clock cycle, dispatching each of the operations to distinct instruction issue queues during the same clock cycle.

Abstract: Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.

Abstract: Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.

Abstract: Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.