Patents by Inventor Kurt A. Olson
Kurt A. Olson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20080318432Abstract: A reactor for processing semiconductor wafers with electrodes and other surfaces that can be one of heated, textured and/or pre-coated in order to facilitate adherence of materials deposited thereon, and eliminate the disadvantages resulting from the spaulding, flaking and/or delaminating of such materials which can interfere with semiconductor wafer processing.Type: ApplicationFiled: September 2, 2008Publication date: December 25, 2008Applicant: TEGAL CORPORATIONInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Kurt A. Olson
-
Patent number: 7223699Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: GrantFiled: March 23, 2005Date of Patent: May 29, 2007Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C Vail, Kurt A. Olson
-
Patent number: 6905969Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: GrantFiled: May 28, 2002Date of Patent: June 14, 2005Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
-
Patent number: 6774046Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.Type: GrantFiled: June 13, 2001Date of Patent: August 10, 2004Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Alferd Cofer, Leslie G. Jerde, Kurt A. Olson, Paritosh Rajora
-
Patent number: 6620335Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: GrantFiled: December 7, 1999Date of Patent: September 16, 2003Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
-
Patent number: 6500314Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: GrantFiled: July 3, 1996Date of Patent: December 31, 2002Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
-
Publication number: 20020139665Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: ApplicationFiled: May 28, 2002Publication date: October 3, 2002Applicant: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
-
Patent number: 6354240Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: GrantFiled: September 11, 1998Date of Patent: March 12, 2002Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
-
Publication number: 20010031561Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.Type: ApplicationFiled: June 13, 2001Publication date: October 18, 2001Applicant: Tegal CorporationInventors: Stephen P. DeOrnellas, Alferd Cofer, Leslie G. Jerde, Kurt A. Olson, Paritosh Rajora
-
Patent number: 6046116Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.Type: GrantFiled: November 19, 1997Date of Patent: April 4, 2000Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Alfred Cofer, Leslie G. Jerde, Kurt A. Olson, Paritosh Rajora
-
Patent number: 5548470Abstract: An electrostatic chuck (ESC) provides increased temperature uniformity and adjustment capability of the surface of a wafer or wafer-like workpiece during processing, for example, in an electron-cyclotron-resonance chemical vapor deposition (ECR-CVD) reactor. Temperature uniformity is achieved through an improved pattern of grooves in the face of the ESC which allows an inert gas to be contained between the ESC and a wafer held thereby even at high levels of vacuum. The ESC is adapted for a particular desired temperature range by choice of surface roughness of the remaining areas of the face of the ESC. Adjustability within that range is achieved by variation of the electrostatic voltage by which a wafer is held against the chuck face.Type: GrantFiled: July 19, 1994Date of Patent: August 20, 1996Assignee: International Business Machines CorporationInventors: Anwar Husain, David E. Kotecki, Stephan E. Lassig, Kurt A. Olson, Anthony J. Ricci