Abstract: Disclosed are embodiments of an improved design method, the results of which are a final design structure for an integrated circuit that incorporates, not only layout information, but also client-specific manufacturing information (e.g., import/export information, service requests, processing directives, purchase order requirements, design rule information, etc.) in the same data format in hierarchical form. Also disclosed are embodiments of a manufacturing control method and system. In these embodiments, a final design structure, such as that described above, is received at tape-in. The information contained therein (particularly, the client-specific manufacturing information) is sorted by type and then forwarded to the appropriate tools within the manufacturing facility for processing.

Abstract: Disclosed are embodiments of an improved design method, the results of which are a final design structure for an integrated circuit that incorporates, not only layout information, but also client-specific manufacturing information (e.g., import/export information, service requests, processing directives, purchase order requirements, design rule information, etc.) in the same data format in hierarchical form. Also disclosed are embodiments of a manufacturing control method and system. In these embodiments, a final design structure, such as that described above, is received at tape-in. The information contained therein (particularly, the client-specific manufacturing information) is sorted by type and then forwarded to the appropriate tools within the manufacturing facility for processing.

Abstract: An critical interconnect line (300) for an integrated circuit is provided in which the problem of dishing of copper is addressed. An interconnect line (300) is provided for an integrated circuit in the form of a critical interconnect line modelled as a transmission line. The interconnect line (300) is formed of a conductive material having a width (302) and a length (303). The interconnect line (300) comprises at least two fingers (304, 305, 306) extending the length (303) of the interconnect line (300), an elongate aperture (309) in the conductive material separating two adjacent fingers (304, 305, 306), and one or more bridges (308) joining the fingers (304, 305, 306) at intervals along the length (303) of the interconnect line (300). The fingers (303, 304, 305) are kept within a width for which the effect of dishing acceptable width whilst the bridges (307, 308) keep the fingers (304, 305, 306) at the same potential difference.

Abstract: Described herein is a method for selectively enlarging vias connecting two different layers of conductors in a semiconductor device. Whether or not an individual via is extended on each of its edges is determined by the distance of the edge to the neighboring features. Since many vias can be selectively enlarged along one or more edges without infringing upon neighboring structures, via integrity and conductive characteristics are improved.

Abstract: A copper-interconnect, low-K dielectric integrated circuit has reduced corrosion of the interconnect when the crackstop next to the kerf is also used as the primacy barrier to oxygen diffusion through the dielectric, with corresponding elements of the crackstop being constructed simultaneously with the circuit interconnect elements; e.g. horizontal interconnect elements have a corresponding structure in the crackstop and vias between interconnect layers have corresponding structures in the crackstop.