Abstract: Disclosed are methods and apparatus for sampling defects. A test chip having a plurality of test structures is provided that is designed so that defect sampling may be customized to obtain different critical areas from the test chip. Each test structure is conceptually divided into a plurality of unit cells (e.g., a pair of grounded and floating conductive lines). The defects of a percentage of unit cells may then be sampled for each test structure to conceptually form a sub test structure that has a different size than the original test structure. The percentage of unit cells that are sampled for each test structure is chosen so as to achieve a specific critical area curve. The defects from each sampled set of unit cells may then combined to determine yield for a product chip having the same specific critical area curve.

Abstract: Disclosed are methods and apparatus for automatically filtering out physical defects from electrical defects that are found during a voltage contrast inspection of a test structure on a semiconductor device.

Abstract: Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element. In another embodiment, a semiconductor die having a scanning area is disclosed.

Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Abstract: Disclosed are methods and apparatus for determining whether to perform burn-in on a semiconductor product, such as a product wafer or product wafer lot. In general terms, test structures on the semiconductor product are inspected to extract yield information, such as defect densities. Since this yield information is related to the early or extrinsic instantaneous failure rate, one may then determine the instantaneous extrinsic failure rate for one or more failure mechanisms, such as electromigration, gate oxide breakdown, or hot carrier injection, based on this yield information. It is then determined whether to perform burn-in on the semiconductor product based on the determined instantaneous failure rate.

Abstract: An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure.

Abstract: An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure.

Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Abstract: Disclosed are methods and apparatus for automatically filtering out physical defects from electrical defects that are found during a voltage contrast inspection of a test structure on a semiconductor device. In general terms, the test structure is designed to include a plurality of features that will charge to specific voltage potentials when scanned with an electron beam during a voltage contrast inspection. Images of the scanned features are generated, and the relative brightness level of each feature depends on the corresponding potential on such feature. That is, some features are expected to appear dark, and other features are expected to appear bright. If there is no defect present in the scanned feature, the corresponding image will have the expected number of bright and dark features. However, if there is a defect present, the number of dark and bright features within the generated image will not match expected results.

Abstract: Disclosed are methods and apparatus for detecting defects in a partially fabricated semiconductor device with self-aligned contacts. The self-aligned contacts are formed from a first layer with a plurality of contact portions, a second layer with a plurality of conductive lines that are each aligned proximate to an associated underlying contact portion, and a third insulating layer formed over the conductive lines and their proximate underlying contact portions. The third insulating layer has a plurality of vias formed therein that are each formed alongside a one of the conductive lines and over its proximate underlying contact portion. A charged particle beam is scanned over a portion of the vias to form a voltage contrast image of each via. When a minority of the vias in the image have a significantly different brightness level than a majority of the vias, it is then determined that the minority of vias have defects.

Abstract: A process for fabricating lightly-doped-drains (LDD) for short-channel metal oxide semiconductor (MOS) transistors. The process utilizes a pulsed laser process to incorporate the dopants, thus eliminating the prior oxide deposition and etching steps. During the process, the silicon in the source/drain region is melted by the laser energy. Impurities from the gas phase diffuse into the molten silicon to appropriately dope the source/drain regions. By controlling the energy of the laser, a lightly-doped-drain can be formed in one processing step. This is accomplished by first using a single high energy laser pulse to melt the silicon to a significant depth and thus the amount of dopants incorporated into the silicon is small. Furthermore, the dopants incorporated during this step diffuse to the edge of the MOS transistor gate structure. Next, many low energy laser pulses are used to heavily dope the source/drain silicon only in a very shallow region.

Abstract: Silicon device structures designed to allow measurement of important doping process parameters immediately after the doping step has occurred. The test structures are processed through contact formation using standard semiconductor fabrication techniques. After the contacts have been formed, the structures are covered by an oxide layer and an aluminum layer. The aluminum layer is then patterned to expose the contact pads and selected regions of the silicon to be doped. Doping is then performed, and the whole structure is annealed with a pulsed excimer laser. But laser annealing, unlike standard annealing techniques, does not effect the aluminum contacts because the laser light is reflected by the aluminum. Once the annealing process is complete, the structures can be probed, using standard techniques, to ascertain data about the doping step.

Abstract: A method for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon.

Abstract: A doping sequence that reduces the cost and complexity of forming source/drain regions in complementary metal oxide silicon (CMOS) integrated circuit technologies. The process combines the use of patterned excimer laser annealing, dopant-saturated spin-on glass, silicide contact structures and interference effects creates by thin dielectric layers to produce source and drain junctions that are ultrashallow in depth but exhibit low sheet and contact resistance. The process utilizes no photolithography and can be achieved without the use of expensive vacuum equipment. The process margins are wide, and yield loss due to contact of the ultrashallow dopants is eliminated.

Abstract: A process for forming retrograde and oscillatory profiles in crystalline and polycrystalline silicon. The process consisting of introducing an n- or p-type dopant into the silicon, or using prior doped silicon, then exposing the silicon to multiple pulses of a high-intensity laser or other appropriate energy source that melts the silicon for short time duration. Depending on the number of laser pulses directed at the silicon, retrograde profiles with peak/surface dopant concentrations which vary from 1-1e4 are produced. The laser treatment can be performed in air or in vacuum, with the silicon at room temperature or heated to a selected temperature.

Abstract: A method in which a thin layer of semiconducting, insulating, or metallic material is transferred by ablation from a source substrate, coated uniformly with a thin layer of said material, to a target substrate, where said material is desired, with a pulsed, high intensity, patternable beam of energy. The use of a patternable beam allows area-selective ablation from the source substrate resulting in additive deposition of the material onto the target substrate which may require a very low percentage of the area to be covered. Since material is placed only where it is required, material waste can be minimized by reusing the source substrate for depositions on multiple target substrates. Due to the use of a pulsed, high intensity energy source the target substrate remains at low temperature during the process, and thus low-temperature, low cost transparent glass or plastic can be used as the target substrate.

Abstract: A method or process of crystallizing and doping amorphous silicon (a-Si) on a low-temperature plastic substrate using a short pulsed high energy source in a selected environment, without heat propagation and build-up in the substrate. The pulsed energy processing of the a-Si in a selected environment, such as BF3 and PF5, will form a doped micro-crystalline or poly-crystalline silicon (pc-Si) region or junction point with improved mobilities, lifetimes and drift and diffusion lengths and with reduced resistivity. The advantage of this method or process is that it provides for high energy materials processing on low cost, low temperature, transparent plastic substrates. Using pulsed laser processing a high (>900.degree. C.), localized processing temperature can be achieved in thin films, with little accompanying temperature rise in the substrate, since substrate temperatures do not exceed 180.degree. C. for more than a few microseconds.

Abstract: The present invention comprises a method of selective epitaxy on a semiconductor substrate. The present invention provides a method of selectively forming high quality, thin GeSi layers in a silicon circuit, and a method for fabricating smaller semiconductor chips with a greater yield (more error free chips) at a lower cost. The method comprises forming an upper layer over a substrate, and depositing a reflectivity mask which is then removed over selected sections. Using a laser to melt the unmasked sections of the upper layer, the semiconductor material in the upper layer is heated and diffused into the substrate semiconductor material. By varying the amount of laser radiation, the epitaxial layer is formed to a controlled depth which may be very thin. When cooled, a single crystal epitaxial layer is formed over the patterned substrate. The present invention provides the ability to selectively grow layers of mixed semiconductors over patterned substrates such as a layer of Ge.sub.x Si.sub.

Abstract: The fabrication of bipolar junction transistors in silicon-on-sapphire (SOS) relies upon the laser-assisted dopant activation in SOS. A patterned 100% aluminum mask whose function is to reflect laser light from regions where melting of the silicon is undesirable is provided on an SOS wafer to be processed. The wafer is placed within a wafer carrier that is evacuated and backfilled with an inert atmosphere and that is provided with a window transparent to the wavelength of the laser beam to allow illumination of the masked wafer when the carrier is inserted into a laser processing system. A pulsed laser (typically an excimer laser) beam is appropriately shaped and homogenized and one or more pulses are directed onto the wafer. The laser beam pulse energy and pulse duration are set to obtain the optimal fluence impinging on the wafer in order to achieve the desired melt duration and corresponding junction depth.