Abstract: In multi-display systems, such as video walls, comprising a control computing system providing content to multiple display computing systems driving a plurality of displays, the refresh rates of the displays can drift over time. This drift can introduce display artifacts, which can make for an unpleasant viewing experience. To counteract display refresh drift, a control system periodically compares display refresh timestamps of the individual display systems to a reference display refresh timestamp of a reference display system. If the difference exceeds a threshold, the control system determines clock adjustment information that is sent to the display system exhibiting drift. The display system utilizes the clock adjustment information to adjust the frequency of a display system clock, which can be done by writing the clock adjustment information to registers that control the behavior of a phase-locked loop that generates the clock used by display refresh circuitry.

Abstract: Apparatuses, storage media and methods associated with computer assisted or autonomous driving (CA/AD), are disclosed herein. In some embodiments, an apparatus includes an interconnect to mate a pluggable compute module with an in-vehicle compute hub disposed in a vehicle to form an upgradable vehicle compute system for the vehicle, the interconnect having a fixed section and a configurable section. The fixed section includes a dynamic power delivery interface, and a management channel. The configurable section includes a plurality of configurable input/output (I/O) interfaces. Other embodiments are also described and claimed.

Abstract: Apparatuses, storage media and methods associated with computer assisted or autonomous driving (CA/AD), are disclosed herein. In some embodiments, an apparatus includes an interconnect to mate a pluggable compute module with an in-vehicle compute hub disposed in a vehicle to form an upgradable vehicle compute system for the vehicle, the interconnect having a fixed section and a configurable section. The fixed section includes a dynamic power delivery interface, and a management channel. The configurable section includes a plurality of configurable input/output (I/O) interfaces. Other embodiments are also described and claimed.

Abstract: A customizable computing system, having a microprocessor and a programmable logic device coupled to the microprocessor via a dedicated bus. The programmable logic device includes a configuration to provide I/O functionality to the system and may be a field programmable gate array. The programmable logic device operates as both a north bridge and a south bridge as is understood by those of ordinary skill in the art. Requests are received from the microprocessor in the programmable logic device over the dedicated bus and are processor specific requests. The processor specific requests are translated into processor dependent commands by a bridge. After the processor specific requests are translated into processor dependent commands, the commands are forwarded to processor independent I/O structures which interface with both internal and external peripheral devices to the customizable computing system.