Abstract: A semiconductor package utilizing a carrier with substantially parallel top and bottom surfaces having a recess in the bottom surface and a slot in the top surface communicating with the recess in the bottom surface and provided with electrical conductors on its top surface is provided with an integrated semiconductor chip having a major surface and contact pads on the major surface in the recess of the carrier, with said contact pads positioned in the region of said slot so that the contact pads can be connected by lead wires passing through said slot, to the conductors on the top side of the carrier. The active surface of the chip containing the contact pads is encapsulated but the back surface of the chip and carrier is left exposed to improve the thermal characteristics of the chip while maintaining a low package profile.

Abstract: An electronic package (11) which comprises a substrate (12) having several chips (13) arranged thereon, and a plurality of connector pins (26) fitted in pin plates (21-24) and electrically connected via conductors to the chips (13). Each pin plate is mounted by means of at least one flexible connector element (29) connected to the conductors at a respective peripheral section (16-19) of the substrate (12). The pin plates have a base surface in the form of any discretionary polygon, in such a manner that, when folded, form a plane substantially flush with the plane of the substrate (12) into a position beneath the substrate (12), or vice versa. Thus an electronic package is obtained which is less complex in its manufacture and covers a considerably reduced base surface while offering a comparable performance.