Patents by Inventor Kurt Knorpp
Kurt Knorpp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9111645Abstract: Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.Type: GrantFiled: July 17, 2009Date of Patent: August 18, 2015Assignee: Rambus Inc.Inventors: Kishore Ven Kasamsetty, Wayne S. Richardson, Kurt Knorpp, Frederick A. Ware
-
Publication number: 20110126081Abstract: Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.Type: ApplicationFiled: July 17, 2009Publication date: May 26, 2011Applicant: RAMBUS INC.Inventors: Kishore Ven Kasamsetty, Wayne S. Richardson, Kurt Knorpp, Frederick A. Ware
-
Publication number: 20070268765Abstract: An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.Type: ApplicationFiled: August 7, 2007Publication date: November 22, 2007Inventors: Steven Woo, Michael Ching, Chad Bellows, Wayne Richardson, Kurt Knorpp, Jun Kim
-
Publication number: 20060067146Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation.Type: ApplicationFiled: September 30, 2004Publication date: March 30, 2006Inventors: Steven Woo, Michael Ching, Chad Bellows, Wayne Richardson, Kurt Knorpp, Jun Kim
-
Publication number: 20050248383Abstract: A pulse multiplexed output subsystem is disclosed. In one particular exemplary embodiment, the output subsystem may comprise a plurality of pulse generators, a first pair of transistors, and a second pair of transistors, wherein each of the first pair of transistors is coupled to a respective one of a first pair of the plurality of pulse generators, and wherein each of the second pair of transistors is coupled to a respective one of a second pair of the plurality of pulse generators. The output subsystem may also comprise a first pair of resistive loads, wherein each of the first pair of resistive loads is coupled to a respective one of the first pair of transistors and a respective one of the second pair of transistors, and a first current source coupled to the first pair of transistors and the second pair of transistors.Type: ApplicationFiled: May 6, 2005Publication date: November 10, 2005Inventors: Wayne Fang, Wayne Richardson, Kurt Knorpp
-
Publication number: 20050237094Abstract: An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current 5 river receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.Type: ApplicationFiled: June 8, 2005Publication date: October 27, 2005Inventors: Donald Stark, Jun Kim, Kurt Knorpp, Michael Ching, Natsuki Kushiyama
-
Patent number: 6754120Abstract: Described are memory systems designed to emphasize differences between memory-cell access times. As a consequence of these access-time variations, data read from different memory cells arrives at some modified output circuitry. The output circuitry sequentially offloads the data in the order of arrival. Data access times are reduced because the output circuitry can begin shifting the first data to arrive before the slower data is ready for capture. Differences between data access times for cells in a given memory array may be emphasized using differently sized sense amplifiers, routing, or both.Type: GrantFiled: February 11, 2003Date of Patent: June 22, 2004Assignee: Rambus Inc.Inventors: Chad Bellows, Wayne Richardson, Lawrence Lai, Kurt Knorpp
-
Patent number: 6295242Abstract: A current sensing, cascadable differential amplifier has a special bias circuit that provides a low impedance input and a high impedance output, whereby plural stages may be connected in cascade. Optionally, active current sources are used as pull-ups for the data lines, to increase the output impedance and improve the data line common mode level. The amplifier performs as a current sensing sense amplifier in a large scale, fast access semiconductor means and in this application, the memory does not need equalizing clock signals, nor is the access time slowed materially in the plural cascade stages.Type: GrantFiled: September 27, 1996Date of Patent: September 25, 2001Assignee: Sony Electronics, Inc.Inventors: Lee-Lean Shu, Kurt Knorpp, Katsunori Seno
-
Patent number: 5519712Abstract: A test circuit for a single chip semiconductor memory array, located in the chip, enables testing of all columns along a word lines without additional column readout circuits. A pair of current detecting differential amplifiers are connected to the bit lines of multiple memory cells along a word line, and the amplifier outputs are compared to generate a pass/fail signal during a read access.Type: GrantFiled: October 12, 1994Date of Patent: May 21, 1996Assignee: Sony Electronics, Inc.Inventors: Lee-Lean Shu, Kurt Knorpp, Katsunori Seno
-
Patent number: 5457407Abstract: An output buffer comprises a reference circuit having a plurality of reference transistors connected in parallel to each other and a output driver circuit having a corresponding plurality of driver transistors connected in parallel with each other. The reference transistors and the driver transistors both have varying widths with the widths of the reference transistors being a binary fraction, for instance one fourth, smaller than the widths of the corresponding output driver transistors. The transistors in the reference circuit are selectively conducted in order to match an impedance of the reference transistors to the impedance of a user selected resistor, representing a fraction of the impedance of a transmission line. The selection of the reference transistors also determines the selection of the driver transistors and consequently causes the impedance of the output driver to match the impedance of the transmission line.Type: GrantFiled: July 6, 1994Date of Patent: October 10, 1995Assignee: Sony Electronics Inc.Inventors: Lee-Lean Shu, Kurt Knorpp
-
Patent number: 5384503Abstract: A current sensing, cascadable differential amplifier has a special bias circuit that provides a low impedance input and a high impedance output, whereby plural stages may be connected in cascade. Optionally, active current sources are used as pull-ups for the data lines, to increase the output impedance and improve the data line common mode level. The amplifier performs as a current sensing sense amplifier in a large scale, fast access semiconductor memory and in this application, the memory does not need equalizing clock signals, nor is the access time slowed materially in the plural cascade stages.Type: GrantFiled: September 9, 1992Date of Patent: January 24, 1995Inventors: Lee-Lean Shu, Kurt Knorpp, Katsunori Seno
-
Patent number: 5327382Abstract: In a single chip semiconductor memory, having independent memory areas for normal memory cells and redundant memory cells, the redundant cells are tested in a parallel or multi-bit test mode simultaneously with the normal cells they replace, by enabling the redundant memory area in response to simultaneous detection of the state of the multi-bit test mode, the presence of a programmed redundant bit for a memory cell under test, and the operative selection of the normal memory matrix.Type: GrantFiled: September 9, 1992Date of Patent: July 5, 1994Inventors: Katsunori Seno, Kurt Knorpp