Abstract: Managing feedthrough wiring for an integrated circuit via design data is provided. The integrated circuit includes a sub-unit, which further includes a feedthrough wire that forwards a digital signal from an input of the sub-unit to an output of the sub-unit. The design data describes the feedthrough wiring of the sub-unit. Management of the feedthrough wiring includes determining physical constraint data from parameter data of the feedthrough wire and timing constraint data related to the feedthrough wire from the physical constraint data. The design data is then synthesized based on the timing constraint data.

Abstract: Managing feedthrough wiring for an integrated circuit via design data is provided. The integrated circuit includes a sub-unit, which further includes a feedthrough wire that forwards a digital signal from an input of the sub-unit to an output of the sub-unit. The design data describes the feedthrough wiring of the sub-unit. Management of the feedthrough wiring includes determining physical constraint data from parameter data of the feedthrough wire and timing constraint data related to the feedthrough wire from the physical constraint data. The design data is then synthesized based on the timing constraint data.

Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: A semiconductor circuit is provided having a crossbar switch arrangement, which includes at least one multiplexer, an output of which corresponds to an output of the crossbar switch arrangement. The arrangement also includes: a set of input lines connected to data inputs of the multiplexer, the input lines extending along a first direction of the semiconductor circuit; and a set of select lines connected to select inputs of the multiplexer, the select lines extending along a second direction of the semiconductor circuit, where the second direction differs from the first direction. The multiplexer includes at least one multiplexing circuit for generating a multiplexed signal from signals present at the input lines and at least one primary output driver for generating an output signal from the multiplexed signal.

Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: A facility is provided for automatically generating design data for a semiconductor circuit including a crossbar switch. The method includes synthesizing the crossbar switch using predefined multiplexer building blocks, where the predefined multiplexer building blocks include at least a multiplexer, an input driver and a select driver. In addition, the method includes regularly placing the predefined multiplexer building blocks to define a crossbar switch arrangement, testing the crossbar switch arrangement for timing constraints and re-synthesizing the crossbar switch and/or replacing the predefined multiplexer building blocks based on the testing.

Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: A facility is provided for automatically generating design data for a semiconductor circuit including a crossbar switch. The method includes synthesizing the crossbar switch using predefined multiplexer building blocks, where the predefined multiplexer building blocks include at least a multiplexer, an input driver and a select driver. In addition, the method includes regularly placing the predefined multiplexer building blocks to define a crossbar switch arrangement, testing the crossbar switch arrangement for timing constraints and re-synthesizing the crossbar switch and/or replacing the predefined multiplexer building blocks based on the testing.

Abstract: A semiconductor circuit is provided having a crossbar switch arrangement, which includes at least one multiplexer, an output of which corresponds to an output of the crossbar switch arrangement. The arrangement also includes: a set of input lines connected to data inputs of the multiplexer, the input lines extending along a first direction of the semiconductor circuit; and a set of select lines connected to select inputs of the multiplexer, the select lines extending along a second direction of the semiconductor circuit, where the second direction differs from the first direction. The multiplexer includes at least one multiplexing circuit for generating a multiplexed signal from signals present at the input lines and at least one primary output driver for generating an output signal from the multiplexed signal.

Abstract: An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data.

Abstract: Automated analyzing of an endpoint report for a design of an electronic circuit is provided, which includes: identifying, by a processing device, that one or more test points of a selected path of the endpoint report are associated with one or more inverter devices of an inverter chain of the design of the electronic circuit; establishing, by the processing device, a chain criticality value for the inverter chain; and determining, by the processing device, whether to identify the inverter chain as a dispensable inverter chain, the determining using, at least in part, the chain criticality value for the inverter chain. The establishing may include updating the chain criticality value for each inverter device of the inverter chain, where the chain criticality value is a summed value obtained from criticality values for the one or more inverter devices of the inverter chain.

Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: Automated analyzing of an endpoint report for a design of an electronic circuit is provided, which includes: identifying, by a processing device, that one or more test points of a selected path of the endpoint report are associated with one or more inverter devices of an inverter chain of the design of the electronic circuit; establishing, by the processing device, a chain criticality value for the inverter chain; and determining, by the processing device, whether to identify the inverter chain as a dispensable inverter chain, the determining using, at least in part, the chain criticality value for the inverter chain. The establishing may include updating the chain criticality value for each inverter device of the inverter chain, where the chain criticality value is a summed value obtained from criticality values for the one or more inverter devices of the inverter chain.

Abstract: An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data.

Abstract: An end point report is created from a comprehensive timing report following steps that include: receiving a comprehensive timing report for an electronic circuit, determining a timing data set for a start pin, determining a worst timing path that includes the start pin based, at least in part, upon the comprehensive timing report, and generating an end point report for the worst timing path.

Abstract: An end point report is created from a comprehensive timing report following steps that include: receiving a comprehensive timing report for an electronic circuit, determining a timing data set for a start pin, determining a worst timing path that includes the start pin based, at least in part, upon the comprehensive timing report, and generating an end point report for the worst timing path.

Abstract: An improved method for fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro comprises: Loading hardware design timing data to determine pins where an early mode slack fix can be applied to fix an early mode slack; for each such pin determining a location across the design hierarchy for the early mode slack fix by calculating a weight value for each of a selection of fix locations of the early mode slack based on absolute values of arrival times of data signals, ratio and difference between arrival times of late mode data signals and early mode data signals; and assigning the early mode slack fix to the determined location based on said weight value.

Abstract: An improved method for fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro comprises: Loading hardware design timing data to determine pins where an early mode slack fix can be applied to fix an early mode slack; for each such pin determining a location across the design hierarchy for the early mode slack fix by calculating a weight value for each of a selection of fix locations of the early mode slack based on absolute values of arrival times of data signals, ratio and difference between arrival times of late mode data signals and early mode data signals; and assigning the early mode slack fix to the determined location based on said weight value.

Abstract: Some example embodiments include an apparatus for comparing a first operand to a second operand. The apparatus includes a SIMD accelerator configured to compare first multiple parts (e.g., bytes) of first operand to second multiple parts (e.g., bytes) of the second operand. The SIMD accelerator includes a ones' complement subtraction logic and a twos' complement logic configured to perform logic operations on the multiple parts of the first operand and the multiple parts of the second operand to generate a group of carry out and propagate data across bits of the multiple parts. At least a portion of the group of carry out and propagate data is reused in the group of logic operations.

Abstract: A computer-readable storage storing instructions for a processor. Execution of the instructions causes loading unit timing data descriptive of an upper hierarchy. Execution of the instructions cause the loading of a unit timing path, and the loading of macro timing data into the memory. Execution of the instructions further cause the replacement of at least a portion of the unit timing report with the macro timing data, and computation of arrival times, slacks, and slews. Execution of the instructions also cause computation of path statistics in accordance with the arrival times, slacks and slews, and generation of a end point report for the unit timing path, including path statistics.