Patents by Inventor Kurt Matoy

Kurt Matoy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10439062
    Abstract: A method of fabricating a semiconductor device includes etching a first surface of a semiconductor substrate from a first side using a first etching process to expose a second surface. The second surface includes a first plurality of features. The first plurality of features has an average height that is a first height. The second surface of the semiconductor substrate is etched from the first side using a second etching process to expose a third surface of the semiconductor substrate. The second etching process converts the first plurality of features into a second plurality of features. The second plurality of features has an average height that is a second height. The second height is less than the first height. A conductive layer is formed over the third surface of the semiconductor substrate using a physical deposition process.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies AG
    Inventors: Bernhard Goller, Kurt Matoy
  • Publication number: 20190157259
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.
    Type: Application
    Filed: December 31, 2018
    Publication date: May 23, 2019
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
  • Patent number: 10186508
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
  • Publication number: 20180366427
    Abstract: A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 20, 2018
    Inventors: Michael Rogalli, Johann Gatterbauer, Wolfgang Lehnert, Kurt Matoy, Evelyn Napetschnig, Manfred Schneegans, Bernhard Weidgans
  • Publication number: 20180114788
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.
    Type: Application
    Filed: October 24, 2017
    Publication date: April 26, 2018
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
  • Publication number: 20180076321
    Abstract: A method of fabricating a semiconductor device includes etching a first surface of a semiconductor substrate from a first side using a first etching process to expose a second surface. The second surface includes a first plurality of features. The first plurality of features has an average height that is a first height. The second surface of the semiconductor substrate is etched from the first side using a second etching process to expose a third surface of the semiconductor substrate. The second etching process converts the first plurality of features into a second plurality of features. The second plurality of features has an average height that is a second height. The second height is less than the first height. A conductive layer is formed over the third surface of the semiconductor substrate using a physical deposition process.
    Type: Application
    Filed: September 9, 2016
    Publication date: March 15, 2018
    Inventors: Bernhard Goller, Kurt Matoy
  • Patent number: 9728480
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies AG
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Silvana Fister, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Publication number: 20160133584
    Abstract: According to various embodiments, a semiconductor device may include: a contact pad; a metal clip disposed over the contact pad; and a porous metal layer disposed between the metal clip and the contact pad, the porous metal layer connecting the metal clip and the contact pad with each other.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 12, 2016
    Inventors: Martin Mischitz, Kurt Matoy
  • Publication number: 20160126197
    Abstract: A semiconductor device includes a semiconductor chip having a first main surface and a second main surface. A chip electrode is disposed on the first main surface. The chip electrode includes a first metal layer and wherein the first metal layer is arranged between the semiconductor chip and the second metal layer.
    Type: Application
    Filed: November 4, 2015
    Publication date: May 5, 2016
    Applicant: Infineon Technologies AG
    Inventors: Kurt Matoy, Dirk Ahlers, Ulrike Fastner, Petra Fischer, Karl-Heinz Gasser, Stephan Henneck, Stefan Krivec, Florian Weilnboeck
  • Publication number: 20150235917
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Application
    Filed: April 29, 2015
    Publication date: August 20, 2015
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Silvana Fister, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Patent number: 9006899
    Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Infineon Technologies AG
    Inventors: Paul Ganitzer, Kurt Matoy, Martin Sporn, Mark Harrison
  • Publication number: 20140167270
    Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Paul Ganitzer, Kurt Matoy, Martin Sporn, Mark Harrison
  • Publication number: 20140117511
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: Infineon Technologies AG
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Fister Schlemitz Silvana, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Patent number: 8502274
    Abstract: Power transistor cells are formed in a cell array of an integrated circuit. Contact vias may electrically connect a metal structure above the cell array and the power transistor cells. A connecting line electrically connects a first element arranged in the cell array and a second element arranged in a peripheral region. A portion of the connecting line is arranged between the metal structure and the cell array and runs between a first axis and a second axis which are arranged parallel and at a distance to each other. The distance is greater than a width of the connecting line portion. The connecting line portion is tangent to both the first axis and the second axis. Shear-induced material transport along the connecting line is reduced by shortening critical portions or by exploiting grain boundary effects. The reliability of an insulator structure covering the connecting line is increased.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: August 6, 2013
    Assignee: Infineon Technologies AG
    Inventors: Kurt Matoy, Thomas Detzel, Michael Nelhiebel, Arno Zechmann, Stefan Decker, Robert Illing, Sven Gustav Lanzerstorfer, Christian Djelassi, Bernhard Auer, Stefan Woehlert