Abstract: There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.

Abstract: A programmable logic device (PLD) is disclosed, which can efficiently, in a realestate sense, emulate a Mealy state machine. Specifically, there is a PLD which has macrocells which accept signals from two separate logical OR arrays. Where the first array and macrocell produces a latched output signal and the second array and macrocell circuit produces a non-latched output signal.

Abstract: A programmable logic device (PLD) is disclosed for finding a sum of products or other logic equations. Specifically, there is a PLD which has: 1) a programmable logical AND and programmable logical OR arrays/matrices, similar to a field programmable logic array; and 2) the fully programmable OR array has an optimized signal speed path and non-optimized signal speed path.

Abstract: A programmable logic device (PLD) is disclosed which can efficiently, in a real estate sense, emulate a Mealy state machine. Specifically, there is a PLD which has: (1) a programmable logical AND and two programmable logical OR arrays, similar to a field programmable logic array; and (2) one of the two fully programmable OR array generates a next state of the circuit and the second OR array generates an output responsive to both the inputs and the current state.

Abstract: An output driver circuit includes first and second translator circuits and a boosted voltage generator. The output driver circuit is suitable for driving the first and second inputs of a reduced voltage N-channel output stage. The first and second translator circuits each have a power terminal and an input for receiving first and second logic input signals. A boost voltage generator having a boosted voltage output is respectively coupled to the power terminals of the first and second translator circuits. The first translator circuit has an output coupled to the first input of the N-channel output stage for providing a boosted logic output signal in a logic high polarity state. The second translator circuit has an output coupled to the second input of the N-channel output stage for providing a boosted logic output signal in a logic high polarity state. The outputs of the first and second translator circuits are complementary for driving the N-channel output stage to provide a valid output logic signal.

Abstract: A special mode activation circuit is disclosed for activating a special mode circuit within a semiconductor integrated circuit when the voltage of an input signal at an input terminal of the integrated circuit reaches a special high voltage level that is substantially above a low voltage level range of signals normally associated with binary logic levels. The special mode activation circuit comprises a voltage reduction subcircuit, a voltage detection subcircuit, and an active pullup subcircuit. The voltage reduction subcircuit reduces the voltage of the input signal to generate a reduced voltage input signal. The voltage detection subcircuit is responsive to the reduced voltage signal to prevent activation of the special mode circuit when the reduced voltage input signal is less than a preset threshold value and to activate the special mode circuit when reduced voltage input signal exceeds the preset threshold value.

Abstract: An integrated circuit includes a charge pump to provide current at a potential which is greater than a supply potential. An oscillator provides an output to a pair of capacitors. Each capacitor is bypassed respectively by one of a pair of clamp circuits. An output transistor is gated by one of the clamp circuits to maintain a continuous output at an elevated potential, while reducing power loss caused by impedances within the charge pump circuit. By using the charge pump as a source of elevated potential, the circuit layout of the DRAM array is simplified and the potential boosting circuitry can be locataed outside of the array, on the periphery of the integrated circuit. When used with an integrated circuit device, such as a DRAM, the current from the charge pump may be supplied to nodes on isolation devices and nodes on word lines, thereby improving the performance of the DRAM without substantially changing the circuit configuration of the DRAM array.

Abstract: An integrated circuit device includes a charge pump to provide current at a potential which is greater than a supply potential. A potential maintenance circuit gates on when the potential at the output of the charge pump circuit drops to a level which is below V.sub.CC. The potential maintenance circuit permits the charge pump can be bypassed or designed to provide a minimum current output. An overvoltage shutoff circuit permits the charge pump to be effectively bypassed when supply voltage is sufficiently high to make bypass desireable.

Abstract: There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.