Patents by Inventor Kurt W. Bailey

Kurt W. Bailey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240095510
    Abstract: Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Kurt F. Busch, Jeremiah H. Holleman, III, Pieter Vorenkamp, Stephen W. Bailey
  • Patent number: 9779241
    Abstract: Techniques are provided for actively managing secure boot variables. Such techniques include receiving a request from an entity to modify a portion of a basic input/output system (BIOS), the request including a data segment, and verifying that the requesting entity is authorized to modify a portion of the BIOS. In response to verifying that the requesting entity is authorized, the portion of the BIOS is modified based on the received request and the data segment, and a copy of the data segment is stored in a file on a physical memory that is communicatively coupled to the BIOS. If the BIOS is updated, thereby erasing part or all of the secure boot variables that are stored in the BIOS, the record of changes of the secure boot variables along with default authenticated variables may be used to restore the secure boot variables to a state prior to the BIOS update.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 3, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: William E. Jacobs, Kurt W. Bailey
  • Publication number: 20150089209
    Abstract: Techniques are provided for actively managing secure boot variables. Such techniques include receiving a request from an entity to modify a portion of a basic input/output system (BIOS), the request including a data segment, and verifying that the requesting entity is authorized to modify a portion of the BIOS. In response to verifying that the requesting entity is authorized, the portion of the BIOS is modified based on the received request and the data segment, and a copy of the data segment is stored in a file on a physical memory that is communicatively coupled to the BIOS. If the BIOS is updated, thereby erasing part or all of the secure boot variables that are stored in the BIOS, the record of changes of the secure boot variables along with default authenticated variables may be used to restore the secure boot variables to a state prior to the BIOS update.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Applicant: Cisco Technology, Inc.
    Inventors: William E. Jacobs, Kurt W. Bailey
  • Patent number: 4244108
    Abstract: Improved excitation circuitry for a variable reluctance transducer is disclosed which includes a transformer having a primary winding and a secondary winding. Power circuitry coupled to the primary winding induces an AC excitation signal in the secondary winding which is coupled to the transducer. An error detection circuit compares a reference signal with the excitation signal and feeds back an error signal to the power circuitry to compensate for any differences therebetween. In such manner, a constant excitation signal is maintained for the transducer.
    Type: Grant
    Filed: November 19, 1979
    Date of Patent: January 13, 1981
    Assignee: The Valeron Corporation
    Inventors: Kurt W. Bailey, Richard O. Juengel
  • Patent number: 4197650
    Abstract: A part sizing system in which the upper and lower tolerance limits are illuminated on the same bar graph display. Electrical representations of the upper and lower tolerance limits are alternately coupled to the bar graph display so as to superimpose visual indications of both limits on one another, with each limit being distinguishable from each other by different light intensities. In one embodiment this bar graph display is disposed adjacent another bar graph display in the same housing. The other bar graph display is utilized to provide a visual indication of the output of at least one variable reluctance transducer which measures the size of the part under test. Improved transducer excitation circuitry is also provided for insuring accurate measurements.
    Type: Grant
    Filed: August 22, 1978
    Date of Patent: April 15, 1980
    Assignee: The Valeron Corporation
    Inventors: Kurt W. Bailey, Richard O. Juengel