Abstract: A large, 2 wire, 2-1/2D core memory includes four, 1K (1024) by 1280, core frames with 1280 Y conductors each stringing and inductively coupling a column of 1024 cores in each of the four frames and 4K orthogonal X conductors each stringing and inductively coupling one row of 1280 cores. A word position within the memory is defined by 5 pairs of Y conductors, a corresponding X conductor from each frame, and selection of relative current directions in the Y conductors. Reading of a 20 bit word is accomplished with 5 sense amplifiers in four rapid succession read sub-operations. Digit sense conductor noise recovery time is minimized by arranging for balanced, predictable delta noise on each digit sense conductor of a pair and by providing a multiple digit sense conductor pair crossover arrangement which results in a balancing of image current coupling into adjacent digit sense conductor pairs.

Abstract: A large, 2 wire, 21/2D core memory includes four, 1K (1024) by 1280, core frames with 1280 Y conductors each stringing and inductively coupling a column of 1024 cores in each of the four frames and 4K orthogonal X conductors each stringing and inductively coupling one row of 1280 cores. A word position within the memory is defined by 5 pairs of Y conductors, a corresponding X conductor from each frame, and selection of relative current directions in the Y conductors. Reading of a 20 bit word is accomplished with 5 sense amplifiers in four rapid succession read sub-operations. Writing is accomplished in two sub-operations by separately controlling partial select digit currents in each of the 5 pairs of Y conductors. A bidirectional X drive and switching arrangement utilizes overlapping X drive currents and shared circuitry to maximize memory speed and reduce electronic components costs.