Patents by Inventor Kushal DALMIA
Kushal DALMIA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940931Abstract: A turnstile OS primitive is provided that enables support for owner tracking and waiting. The turnstile primitive enables a common framework that can be adopted across multiple different types of synchronization primitives to provide a common service for priority boosting and wait queuing. A turnstile can also provide a mechanism to enable a turnstile to block on another turnstile, allowing multi-hop priority boosting within a chain of multiple blocking turnstiles.Type: GrantFiled: January 5, 2021Date of Patent: March 26, 2024Assignee: Apple Inc.Inventors: Jainam A. Shah, Jeremy C. Andrus, Daniel A. Chimene, Kushal Dalmia, Pierre Habouzit, James M. Magee, Marina Sadini, Daniel A. Steffen
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Publication number: 20230067109Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having two or more central processing unit (CPU) clusters of a first core type and a CPU cluster of a second core type. Some embodiments include determining a control effort for an active thread group, and assigning the thread group to a first performance island according to the control effort range of the first performance island. The first performance island can include a first CPU cluster of the first core type, where a second performance island includes a second CPU cluster of the first core type, where the second performance island corresponds to a different control effort range than the first performance island. Some embodiments include assigning the first CPU cluster as a preferred CPU cluster of the first thread group, and transmitting a first signal identifying the first CPU cluster as the preferred CPU cluster assigned to the first thread group.Type: ApplicationFiled: August 23, 2022Publication date: March 2, 2023Applicant: Apple Inc.Inventors: Bryan R. HINCH, John G. DORSEY, Ronit BANERJEE, Kushal DALMIA, Daniel A. CHIMENE, Jaidev P. PATWARDHAN
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Publication number: 20230040310Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having a first central processing unit (CPU) cluster comprising a first core type, and a second CPU cluster comprising a second core type, where the AMP system can update a thread metric for a first thread running on the first CPU cluster based at least on: a past shared resource overloaded metric of the first CPU cluster, and on-core metrics of the first thread. The on-core metrics of the first thread can indicate that first thread contributes to contention of the same shared resource corresponding to the past shared resource overloaded metric of the first CPU cluster. The AMP system can assign the first thread to a different CPU cluster while other threads of the same thread group remain assigned to the first CPU cluster. The thread metric can include a Matrix Extension (MX) thread flag or a Bus Interface Unit (BIU) thread flag.Type: ApplicationFiled: August 3, 2021Publication date: February 9, 2023Applicant: Apple Inc.Inventors: John G. DORSEY, Bryan R. HINCH, Ronit BANERJEE, Kushal DALMIA, Daniel A. CHIMENE, Jaidev P. PATWARDHAN
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Patent number: 11422857Abstract: Embodiments described herein provide multi-level scheduling for threads in a data processing system. One embodiment provides a data processing system comprising one or more processors, a computer-readable memory coupled to the one or more processors, the computer-readable memory to store instructions which, when executed by the one or more processors, configure the one or more processors to receive execution threads for execution on the one or more processors, map the execution threads into a first plurality of buckets based at least in part on a quality of service class of the execution threads, schedule the first plurality of buckets for execution using a first scheduling algorithm, schedule a second plurality thread groups within the first plurality of buckets for execution using a second scheduling algorithm, and schedule a third plurality of threads within the second plurality of thread groups using a third scheduling algorithm.Type: GrantFiled: May 22, 2020Date of Patent: August 23, 2022Assignee: Apple Inc.Inventors: Kushal Dalmia, Jeremy C. Andrus, Daniel A. Chimene, Nigel R. Gamble, James M. Magee, Daniel A. Steffen
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Publication number: 20220222116Abstract: Memory management in a data processing system can learn one or more behaviors of software processes such as daemon software processes and application processes, and based on information learned about the behaviors, the memory management can adjust how it controls memory usage in the system. For example, a memory management system can learn how software processes react (e.g. how quickly they relaunch) to memory recovery methods, such as system initiated terminations of one or more software processes that are performed to reclaim memory to increase available volatile memory, and based on information about how they react, the memory recovery methods can operate differently depending upon how the software reacted previously.Type: ApplicationFiled: March 21, 2022Publication date: July 14, 2022Inventors: Kushal Dalmia, Andrey V. Talnikov, Lionel D. Desai, Russell A. Blaine
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Patent number: 11301296Abstract: Memory management in a data processing system can learn one or more behaviors of software processes such as daemon software processes and application processes, and based on information learned about the behaviors, the memory management can adjust how it controls memory usage in the system. For example, a memory management system can learn how software processes react (e.g. how quickly they relaunch) to memory recovery methods, such as system initiated terminations of one or more software processes that are performed to reclaim memory to increase available volatile memory, and based on information about how they react, the memory recovery methods can operate differently depending upon how the software reacted previously.Type: GrantFiled: March 3, 2020Date of Patent: April 12, 2022Assignee: Apple Inc.Inventors: Kushal Dalmia, Andrey V. Talnikov, Lionel D. Desai, Russell A. Blaine
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Publication number: 20210157748Abstract: A turnstile OS primitive is provided that enables support for owner tracking and waiting. The turnstile primitive enables a common framework that can be adopted across multiple different types of synchronization primitives to provide a common service for priority boosting and wait queuing. A turnstile can also provide a mechanism to enable a turnstile to block on another turnstile, allowing multi-hop priority boosting within a chain of multiple blocking turnstiles.Type: ApplicationFiled: January 5, 2021Publication date: May 27, 2021Inventors: Jainam A. Shah, Jeremy C. Andrus, Daniel A. Chimene, Kushal Dalmia, Pierre Habouzit, James M. Magee, Marina Sadini, Daniel A. Steffen
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Patent number: 10901920Abstract: One embodiment provides for a computer-implemented method comprising instantiating a synchronization primitive to control access to a resource, acquiring the synchronization primitive at a first thread, the first thread having a first priority, associating a turnstile with the synchronization primitive, setting an inheritor of the turnstile to the first thread, attempting to acquire the synchronization primitive at a second thread while the synchronization primitive is held by the first thread, the second thread having a second priority, adding the second thread to a wait queue of the turnstile; and in response to determining that the second priority is higher than the first priority, increasing the priority of the first thread to the second priority.Type: GrantFiled: April 10, 2019Date of Patent: January 26, 2021Assignee: Apple Inc.Inventors: Jainam A. Shah, Jeremy C. Andrus, Daniel A. Chimene, Kushal Dalmia, Pierre Habouzit, James M. Magee, Marina Sadini, Daniel A. Steffen
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Publication number: 20200379810Abstract: Memory management in a data processing system can learn one or more behaviors of software processes such as daemon software processes and application processes, and based on information learned about the behaviors, the memory management can adjust how it controls memory usage in the system. For example, a memory management system can learn how software processes react (e.g. how quickly they relaunch) to memory recovery methods, such as system initiated terminations of one or more software processes that are performed to reclaim memory to increase available volatile memory, and based on information about how they react, the memory recovery methods can operate differently depending upon how the software reacted previously.Type: ApplicationFiled: March 3, 2020Publication date: December 3, 2020Inventors: Kushal Dalmia, Andrey V. Talnikov, Lionel D. Desai, Russell A. Blaine
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Publication number: 20200379804Abstract: Embodiments described herein provide multi-level scheduling for threads in a data processing system. One embodiment provides a data processing system comprising one or more processors, a computer-readable memory coupled to the one or more processors, the computer-readable memory to store instructions which, when executed by the one or more processors, configure the one or more processors to receive execution threads for execution on the one or more processors, map the execution threads into a first plurality of buckets based at least in part on a quality of service class of the execution threads, schedule the first plurality of buckets for execution using a first scheduling algorithm, schedule a second plurality thread groups within the first plurality of buckets for execution using a second scheduling algorithm, and schedule a third plurality of threads within the second plurality of thread groups using a third scheduling algorithm.Type: ApplicationFiled: May 22, 2020Publication date: December 3, 2020Inventors: Kushal Dalmia, Jeremy C. Andrus, Daniel A. Chimene, Nigel R. Gamble, James M. Magee, Daniel A. Steffen
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Patent number: 10599481Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: GrantFiled: January 12, 2018Date of Patent: March 24, 2020Assignee: Apple Inc.Inventors: Constantin Pistol, Daniel A. Chimene, Jeremy C. Andrus, Russell A. Blaine, Kushal Dalmia
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Publication number: 20190370061Abstract: One embodiment provides for a computer-implemented method comprising instantiating a synchronization primitive to control access to a resource, acquiring the synchronization primitive at a first thread, the first thread having a first priority, associating a turnstile with the synchronization primitive, setting an inheritor of the turnstile to the first thread, attempting to acquire the synchronization primitive at a second thread while the synchronization primitive is held by the first thread, the second thread having a second priority, adding the second thread to a wait queue of the turnstile; and in response to determining that the second priority is higher than the first priority, increasing the priority of the first thread to the second priority.Type: ApplicationFiled: April 10, 2019Publication date: December 5, 2019Inventors: Jainam A. Shah, Jeremy C. Andrus, Daniel A. Chimene, Kushal Dalmia, Pierre Habouzit, James M. Magee, Marina Sadini, Daniel A. Steffen
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Publication number: 20180349177Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.Type: ApplicationFiled: January 12, 2018Publication date: December 6, 2018Inventors: Constantin Pistol, Daniel A. Chimene, Jeremy C. Andrus, Russell A. Blaine, Kushal Dalmia
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Patent number: 9772959Abstract: In one embodiment, input-output (I/O) scheduling system detects and resolves priority inversions by expediting previously dispatched requests to an I/O subsystem. In response to detecting the priority inversion, the system can transmit a command to expedite completion of the blocking I/O request. The pending request can be located within the I/O subsystem and expedited to reduce the pendency period of the request.Type: GrantFiled: May 30, 2014Date of Patent: September 26, 2017Assignee: Apple Inc.Inventors: Russell A. Blaine, Kushal Dalmia, Joseph Sokol, Jr., Andrew W. Vogan, Matthew J. Byom
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Publication number: 20150347327Abstract: In one embodiment, input-output (I/O) scheduling system detects and resolves priority inversions by expediting previously dispatched requests to an I/O subsystem. In response to detecting the priority inversion, the system can transmit a command to expedite completion of the blocking I/O request. The pending request can be located within the I/O subsystem and expedited to reduce the pendency period of the request.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Applicant: Apple Inc.Inventors: Russell A. BLAINE, Kushal DALMIA, Joseph SOKOL, JR., Andrew W. VOGAN, Matthew J. BYOM