Abstract: An integrated circuit device includes a plurality of cells or modules. Each respective one of the cells or modules consumes leakage power, and the amount of leakage power consumed by a respective one of the cells or modules varies depending on states of its inputs. Scan-chain circuitry is configured to propagate through the integrated circuit device, on entry of the integrated circuit device to a low-power mode, a scan-chain pattern created in advance, to apply, to each respective cell or module in the low-power mode, a set of inputs that results in a respective low-power state with reduced leakage power. Creating the scan chain pattern includes identifying respective ones of the cells or modules as having the highest leakage power consumption, and a respective combination of inputs to place each of those the cells or modules in a respective low-power state.

Abstract: A semiconductor device is disclosed that includes, among other things, a computing device including a plurality of transistors, an activity monitor to determine an activity metric associated with the plurality of transistors, and a power controller to, responsive to the activity metric indicating a first activity level, set a power supply voltage for the plurality of transistors to a first value, and responsive to the activity metric indicating a second activity level less than the first activity level, set the power supply voltage to a second value greater than the first value and apply a first reverse back bias voltage to the plurality of transistors to increase a threshold voltage of the plurality of transistors.

Abstract: An integrated circuit and a method of self-testing the integrated circuit are provided. The method comprises: generating a reference voltage at an output of a reference circuit; initiating a test of the reference circuit during a test mode; determining whether the test of the reference circuit passes; and comparing, if the test of the reference circuit passes, a first voltage with the reference voltage. The disclosed test method provides for more complete testing of the integrated circuit.

Abstract: A method and apparatus for testing an electronic device is provided. The method begins when at least one test setup vector for at least one test to be performed is generated. An actual test vector is then generated. The actual test vector may be generated using test results from testing at least one device of known good quality. A delay time parameter determined by waiting for the test controller to complete the test. After the delay time parameter has been determined, at least one test result is output as a test signature. The test signature and the delay time parameter may used to call the test and provide for counter-based delay independent memory testing. The apparatus includes a test controller and a vector memory in communication with the test controller and at least one clock in communication with the test controller and a power supply.

Abstract: An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.

Abstract: An integrated circuit and a method of self-testing the integrated circuit are provided. The method comprises: generating a reference voltage at an output of a reference circuit; initiating a test of the reference circuit during a test mode; determining whether the test of the reference circuit passes; and comparing, if the test of the reference circuit passes, a first voltage with the reference voltage. The disclosed test method provides for more complete testing of the integrated circuit.

Abstract: A voltage regulation subsystem for a microprocessor has both internal and external regulation modes. An internal auxiliary voltage regulator is selectively enabled to overdrive the voltage. The enablement of the auxiliary voltage regulator is contingent upon a comparison of bandgap references of the internal and external regulators used in the respective regulation modes, which boosts the supply voltage, enables circuitry supplied by the external regulator (with the assistance of auxiliary voltage regulators) to boot robustly in extreme Process-Voltage-Temperature (PVT) conditions.

Abstract: A voltage regulation subsystem for a microprocessor has both internal and external regulation modes. An internal auxiliary voltage regulator is selectively enabled to overdrive the voltage. The enablement of the auxiliary voltage regulator is contingent upon a comparison of bandgap references of the internal and external regulators used in the respective regulation modes, which boosts the supply voltage, enables circuitry supplied by the external regulator (with the assistance of auxiliary voltage regulators) to boot robustly in extreme Process-Voltage-Temperature (PVT) conditions.

Abstract: An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.

Abstract: An electronic circuit includes a switchable circuit domain that operates in a RUN mode and a STANDBY mode and receives a supply current from a core power supply. A power regulator is connected between the core power supply and the switchable circuit domain to regulate the supply current provided to the switchable circuit domain when the electronic circuit is in the RUN mode. A capacitor is connected between the power regulator and ground and is charged by a refresh circuit when the electronic circuit is in the STANDBY mode. The refresh circuit maintains a voltage across the capacitor when the electronic circuit is in the standby mode, which reduces the time for the electronic circuit to transition from the STANDBY mode to the RUN mode.

Abstract: A system and method for verifying the electrical behavior of a liquid crystal display (LCD) driver circuit connected to LCD segments of an electronic circuit includes generating test patterns for verifying the LCD driver circuit. The LCD driver circuit generates LCD stimuli in the form of electrical current based on the test patterns. The current is applied to front and back planes of each LCD segment. Root mean square (RMS) voltages of each LCD segment are determined and compared with predetermined threshold values to verify the state of each LCD segment.

Abstract: An electronic circuit includes a switchable circuit domain that operates in a RUN mode and a STANDBY mode and receives a supply current from a core power supply. A power regulator is connected between the core power supply and the switchable circuit domain to regulate the supply current provided to the switchable circuit domain when the electronic circuit is in the RUN mode. A capacitor is connected between the power regulator and ground and is charged by a refresh circuit when the electronic circuit is in the STANDBY mode. The refresh circuit maintains a voltage across the capacitor when the electronic circuit is in the standby mode, which reduces the time for the electronic circuit to transition from the STANDBY mode to the RUN mode.

Abstract: An analog-to-digital converter (ADC) converts an analog input signal to a digital output signal by sampling an analog input signal to obtain an analog sample and then converting the analog sample to the digital output signal using a successive approximation algorithm. The method decreases ADC conversion time and increases ADC throughput.