Patents by Inventor Kushan Vijaykumar VYAS

Kushan Vijaykumar VYAS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10866907
    Abstract: A method comprising, in an image processing operation, identifying location data indicative of a read path for the image processing operation, the read path at least partly traversing a block of pixels of an image. Parameter data relating to a characteristic of the read path in the context of the block is generated from the location. Storage prioritization data is associated with the block at least partly on the basis of the parameter data. The storage prioritization data is for determining whether block data representative of the block is to be evicted from storage.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 15, 2020
    Assignee: Apical Ltd.
    Inventors: Metin Gokhan Ünal, Kushan Vijaykumar Vyas, Robert Shorter, Mario Jose David Manzano
  • Patent number: 10592146
    Abstract: A method of operating a data processing system 4 is disclosed that comprises producing data in the form of blocks of data, where each block of data represents a particular region of a data array, processing the data using a processing operation in which one or more output data values are each determined using data values from plural different lines of the data array, storing the processed data in a memory 21 of the data processing system, and reading the data from the memory 21 in the form of lines.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: March 17, 2020
    Assignee: Arm Limited
    Inventors: Sharjeel Saeed, Kushan Vijaykumar Vyas, Michal Karol Bogusz, Piotr Tadeusz Chrobak, Ozgur Ozkurt
  • Publication number: 20190213141
    Abstract: A method comprising, in an image processing operation, identifying location data indicative of a read path for the image processing operation, the read path at least partly traversing a block of pixels of an image. Parameter data relating to a characteristic of the read path in the context of the block is generated from the location. Storage prioritization data is associated with the block at least partly on the basis of the parameter data. The storage prioritization data is for determining whether block data representative of the block is to be evicted from storage.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 11, 2019
    Inventors: Metin Gokhan ÜNAL, Kushan Vijaykumar VYAS, Robert SHORTER, Mario Jose DAVID MANZANO
  • Patent number: 10210595
    Abstract: A method of operating a data processing system 4 comprises a first processing stage 11, 12 of the data processing system producing data according to a first pattern, and a second processing stage 20 of the data processing system using the data produced by the first processing stage 11, 12 according to a second different pattern. The data processing system 4 deactivates the first processing stage 11, 12 when the first processing stage 11, 12 has produced a set of data that includes sufficient data to allow the set of data to be used by the second processing stage 20 according to the second pattern, and re-activates the first processing stage 11, 12 based on the use of that set of data by the second processing stage 20.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: February 19, 2019
    Assignee: Arm Limited
    Inventors: Sharjeel Saeed, Daren Croxford, Kushan Vijaykumar Vyas
  • Publication number: 20180373432
    Abstract: A method of operating a data processing system 4 is disclosed that comprises producing data in the form of blocks of data, where each block of data represents a particular region of a data array, processing the data using a processing operation in which one or more output data values are each determined using data values from plural different lines of the data array, storing the processed data in a memory 21 of the data processing system, and reading the data from the memory 21 in the form of lines.
    Type: Application
    Filed: June 27, 2017
    Publication date: December 27, 2018
    Applicant: ARM Limited
    Inventors: Sharjeel Saeed, Kushan Vijaykumar Vyas, Michal Karol Bogusz, Piotr Tadeusz Chrobak, Ozgur Ozkurt
  • Patent number: 9805478
    Abstract: Apparatus and a corresponding method for processing image data are provided. The apparatus has compositing circuitry to generate a composite layer for a frame for display from image data representing plural layers of content within the frame. Plural latency buffers are provided to store at least a portion of the image data representing the plural layers. At least one of the plural latency buffers is larger than at least one other of the plural latency buffers. The compositing circuitry is responsive to at least one characteristic of the plural layers of content to allocate the plural layers to respective latency buffers of the plural latency buffers. Image data information for a layer allocated to the larger latency buffer is available for analysis earlier than that of the layers allocated to the smaller latency buffers and processing efficiencies can then result.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: October 31, 2017
    Assignee: ARM Limited
    Inventors: Daren Croxford, Sharjeel Saeed, Kushan Vijaykumar Vyas
  • Publication number: 20170256027
    Abstract: A method of operating a data processing system 4 comprises a first processing stage 11, 12 of the data processing system producing data according to a first pattern, and a second processing stage 20 of the data processing system using the data produced by the first processing stage 11, 12 according to a second different pattern. The data processing system 4 deactivates the first processing stage 11, 12 when the first processing stage 11, 12 has produced a set of data that includes sufficient data to allow the set of data to be used by the second processing stage 20 according to the second pattern, and re-activates the first processing stage 11, 12 based on the use of that set of data by the second processing stage 20.
    Type: Application
    Filed: February 21, 2017
    Publication date: September 7, 2017
    Applicant: ARM Limited
    Inventors: Sharjeel Saeed, Daren Croxford, Kushan Vijaykumar Vyas
  • Publication number: 20160217592
    Abstract: Apparatus and a corresponding method for processing image data are provided. The apparatus has compositing circuitry to generate a composite layer for a frame for display from image data representing plural layers of content within the frame. Plural latency buffers are provided to store at least a portion of the image data representing the plural layers. At least one of the plural latency buffers is larger than at least one other of the plural latency buffers. The compositing circuitry is responsive to at least one characteristic of the plural layers of content to allocate the plural layers to respective latency buffers of the plural latency buffers. Image data information for a layer allocated to the larger latency buffer is available for analysis earlier than that of the layers allocated to the smaller latency buffers and processing efficiencies can then result.
    Type: Application
    Filed: March 11, 2016
    Publication date: July 28, 2016
    Inventors: Daren CROXFORD, Sharjeel SAEED, Kushan Vijaykumar VYAS