Patents by Inventor Kwame Eason

Kwame Eason has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230200063
    Abstract: Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Deepak Thimmegowda, Chang Wan Ha, Md Rezaul Karim Nishat, Liu Liu, Yuanrong Shui, Kwame Eason, Ahmed Reza, Hoon Koh
  • Publication number: 20230084901
    Abstract: A substrate processing system for selectively etching a layer on a substrate includes an upper chamber region, an inductive coil arranged around the upper chamber region and a lower chamber region including a substrate support to support a substrate. A gas distribution device is arranged between the upper chamber region and the lower chamber region and includes a plate with a plurality of holes. A cooling plenum cools the gas distribution device and a purge gas plenum directs purge gas into the lower chamber. A surface to volume ratio of the holes is greater than or equal to 4. A controller selectively supplies an etch gas mixture to the upper chamber and a purge gas to the purge gas plenum and strikes plasma in the upper chamber to selectively etch a layer of the substrate relative to at least one other exposed layer of the substrate.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 16, 2023
    Inventors: Kwame EASON, Dengliang Yang, Pilyeon Park, Faisal Yaqoob, Joon Hong Park, Mark Kawaguchi, Ji Zhu, Ivelin Angelov, Hsiao-Eei Chang
  • Patent number: 11469079
    Abstract: A substrate processing system for selectively etching a layer on a substrate includes an upper chamber region, an inductive coil arranged around the upper chamber region and a lower chamber region including a substrate support to support a substrate. A gas distribution device is arranged between the upper chamber region and the lower chamber region and includes a plate with a plurality of holes. A cooling plenum cools the gas distribution device and a purge gas plenum directs purge gas into the lower chamber. A surface to volume ratio of the holes is greater than or equal to 4. A controller selectively supplies an etch gas mixture to the upper chamber and a purge gas to the purge gas plenum and strikes plasma in the upper chamber to selectively etch a layer of the substrate relative to at least one other exposed layer of the substrate.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: October 11, 2022
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Kwame Eason, Dengliang Yang, Pilyeon Park, Faisal Yaqoob, Joon Hong Park, Mark Kawaguchi, Ivelin Angelov, Ji Zhu, Hsiao-Wei Chang
  • Patent number: 11011388
    Abstract: Methods and apparatus for laterally etching unwanted material from the sidewalls of a recessed feature are described herein. In various embodiments, the method involves etching a portion of the sidewalls, depositing a protective film over a portion of the sidewalls, and cycling the etching and deposition operations until the unwanted material is removed from the entire depth of the recessed feature. Each etching and deposition operation may target a particular depth along the sidewalls of the feature. In some cases, the unwanted material is removed from the bottom of the feature up, and in other cases the unwanted material is removed from the top of the feature down. Some combination of these may also be used.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 18, 2021
    Assignee: Lam Research Corporation
    Inventors: Kwame Eason, Pilyeon Park, Mark Naoshi Kawaguchi, Seung-Ho Park, Hsiao-Wei Chang
  • Publication number: 20190221654
    Abstract: Provided are methods and apparatuses for removing a polysilicon layer on a wafer, where the wafer can include a nitride layer, a low-k dielectric layer, an oxide layer, and other films. A plasma of a hydrogen-based species and a fluorine-based species is generated in a remote plasma source, and the wafer is exposed to the plasma at a relatively low temperature to limit the formation of solid byproduct. In some implementations, the wafer is maintained at a temperature below about 60° C. The polysilicon layer is removed at a very high etch rate, and the selectivity of polysilicon over the nitride layer and the oxide layer is very high. In some implementations, the wafer is supported on a wafer support having a plurality of thermal zones configured to define a plurality of different temperatures across the wafer.
    Type: Application
    Filed: March 26, 2019
    Publication date: July 18, 2019
    Inventors: Dengliang Yang, Kwame Eason, Faisal Yaqoob, Joon Hong Park
  • Publication number: 20190206697
    Abstract: Methods and apparatus for laterally etching unwanted material from the sidewalls of a recessed feature are described herein. In various embodiments, the method involves etching a portion of the sidewalls, depositing a protective film over a portion of the sidewalls, and cycling the etching and deposition operations until the unwanted material is removed from the entire depth of the recessed feature. Each etching and deposition operation may target a particular depth along the sidewalls of the feature. In some cases, the unwanted material is removed from the bottom of the feature up, and in other cases the unwanted material is removed from the top of the feature down. Some combination of these may also be used.
    Type: Application
    Filed: March 7, 2019
    Publication date: July 4, 2019
    Inventors: Kwame Eason, Pilyeon Park, Mark Naoshi Kawaguchi, Seung-Ho Park, Hsiao-Wei Chang
  • Patent number: 10283615
    Abstract: Provided are methods and apparatuses for removing a polysilicon layer on a wafer, where the wafer can include a nitride layer, a low-k dielectric layer, an oxide layer, and other films. A plasma of a hydrogen-based species and a fluorine-based species is generated in a remote plasma source, and the wafer is exposed to the plasma at a relatively low temperature to limit the formation of solid byproduct. In some implementations, the wafer is maintained at a temperature below about 60° C. The polysilicon layer is removed at a very high etch rate, and the selectivity of polysilicon over the nitride layer and the oxide layer is very high. In some implementations, the wafer is supported on a wafer support having a plurality of thermal zones configured to define a plurality of different temperatures across the wafer.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: May 7, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Dengliang Yang, Kwame Eason, Faisal Yaqoob, Joon Hong Park
  • Patent number: 10276398
    Abstract: Methods and apparatus for laterally etching unwanted material from the sidewalls of a recessed feature are described herein. In various embodiments, the method involves etching a portion of the sidewalls, depositing a protective film over a portion of the sidewalls, and cycling the etching and deposition operations until the unwanted material is removed from the entire depth of the recessed feature. Each etching and deposition operation may target a particular depth along the sidewalls of the feature. In some cases, the unwanted material is removed from the bottom of the feature up, and in other cases the unwanted material is removed from the top of the feature down. Some combination of these may also be used.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: April 30, 2019
    Assignee: Lam Research Corporation
    Inventors: Kwame Eason, Pilyeon Park, Mark Naoshi Kawaguchi, Seung-Ho Park, Hsiao-Wei Chang
  • Publication number: 20190043732
    Abstract: Methods and apparatus for laterally etching unwanted material from the sidewalls of a recessed feature are described herein. In various embodiments, the method involves etching a portion of the sidewalls, depositing a protective film over a portion of the sidewalls, and cycling the etching and deposition operations until the unwanted material is removed from the entire depth of the recessed feature. Each etching and deposition operation may target a particular depth along the sidewalls of the feature. In some cases, the unwanted material is removed from the bottom of the feature up, and in other cases the unwanted material is removed from the top of the feature down. Some combination of these may also be used.
    Type: Application
    Filed: August 2, 2017
    Publication date: February 7, 2019
    Inventors: Kwame Eason, Pilyeon Park, Mark Naoshi Kawaguchi, Seung-Ho Park, Hsiao-Wei Chang
  • Patent number: 10147588
    Abstract: A system is provided and includes a substrate processing chamber, one or more injectors, and a controller. The one or more injectors inject an electronegative gas, a baseline electropositive gas, and an additional electropositive gas into the substrate processing chamber. The electronegative gas includes an etch precursor. The additional electropositive gas mixes with and increases electron density of a plasma in the substrate processing chamber. The controller is configured to set an amount, flow rate or pressure of the additional electropositive gas based on at least one of a pressure of the electronegative gas or an electron affinity level of the additional electropositive gas.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: December 4, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Kwame Eason, James Eugene Caron, Ivelin Angelov, Joon Hong Park, Dengliang Yang
  • Publication number: 20180269070
    Abstract: A substrate processing system for selectively etching a layer on a substrate includes an upper chamber region, an inductive coil arranged around the upper chamber region and a lower chamber region including a substrate support to support a substrate. A gas distribution device is arranged between the upper chamber region and the lower chamber region and includes a plate with a plurality of holes. A cooling plenum cools the gas distribution device and a purge gas plenum directs purge gas into the lower chamber. A surface to volume ratio of the holes is greater than or equal to 4. A controller selectively supplies an etch gas mixture to the upper chamber and a purge gas to the purge gas plenum and strikes plasma in the upper chamber to selectively etch a layer of the substrate relative to at least one other exposed layer of the substrate.
    Type: Application
    Filed: March 14, 2017
    Publication date: September 20, 2018
    Inventors: Kwame Eason, Dengliang Yang, Pilyeon Park, Faisal Yaqoob, Joon Hong Park, Mark Kawaguchi, Ivelin Angelov, Ji Zhu, Hsiao-Wei Chang
  • Publication number: 20170236694
    Abstract: A system is provided and includes a substrate processing chamber, one or more injectors, and a controller. The one or more injectors inject an electronegative gas, a baseline electropositive gas, and an additional electropositive gas into the substrate processing chamber. The electronegative gas includes an etch precursor. The additional electropositive gas mixes with and increases electron density of a plasma in the substrate processing chamber. The controller is configured to set an amount, flow rate or pressure of the additional electropositive gas based on at least one of a pressure of the electronegative gas or an electron affinity level of the additional electropositive gas.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 17, 2017
    Inventors: Kwame Eason, James Eugene Caron, Ivelin Angelov, Joon Hong Park, Dengliang Yang
  • Publication number: 20160064519
    Abstract: Provided are methods and apparatuses for removing a polysilicon layer on a wafer, where the wafer can include a nitride layer, a low-k dielectric layer, an oxide layer, and other films. A plasma of a hydrogen-based species and a fluorine-based species is generated in a remote plasma source, and the wafer is exposed to the plasma at a relatively low temperature to limit the formation of solid byproduct. In some implementations, the wafer is maintained at a temperature below about 60° C. The polysilicon layer is removed at a very high etch rate, and the selectivity of polysilicon over the nitride layer and the oxide layer is very high. In some implementations, the wafer is supported on a wafer support having a plurality of thermal zones configured to define a plurality of different temperatures across the wafer.
    Type: Application
    Filed: November 11, 2015
    Publication date: March 3, 2016
    Inventors: Dengliang Yang, Kwame Eason, Faisal Yaqoob, Joon Hong Park