Abstract: The present invention relates to a transmitting device for wireless power transmission, which includes: a bowl-shaped transmitting device body; and a transmitting coil unit for wirelessly transmitting power to a receiving device based on power supplied from a power source. The transmitting coil unit may include a multi-loop coil unit wound in the bottom surface of the transmitting device body, and a helical coil unit wound around the side wall of the transmitting device body, the helical coil unit being wound to increase the radius of a coil loop in a direction to the upper part of the transmitting device body, and being extended from the end of the multi-loop coil unit.

Abstract: A magnetic resonance wireless power transfer method according to an aspect of the present invention includes transmitting power from a source coil to the Tx resonant coil using a magnetic induction method, transmitting the power from the Tx resonant coil to an Rx resonant coil, having a resonant frequency identical with that of the Tx resonant coil, via magnetically-coupled resonance, and transmitting the power from the Rx resonant coil to the device coil of an electronic device using the magnetic induction method. The Tx resonant coil and the Rx resonant coil are arranged at a right angle or a specific angle of inclination relative to each other.

Abstract: A method of operating an integrated circuit is provided. The method includes receiving a data block offset from a second storage device, obtaining a target entry address using the data block offset, and reading an entry among a plurality of entries comprised in a buffer descriptor stored in a first storage device based on the target entry address. The method also includes reading data from a data buffer among a plurality of data buffers included in the first storage device using a physical address included in the entry and transmitting the data to the second storage device.

Abstract: A host includes a cache including a plurality of cache lines, a command descriptor list configured to store a command transmitted from one of the plurality of cache lines, a host controller including a direct memory access (DMA) device that accesses the command descriptor list, and a processor configured to determine a size of the command descriptor list based on a size of the one of the plurality of cache lines.

Abstract: Disclosed are a wireless power transmitter and a method of transmitting power thereof. The wireless power transmitter to wirelessly transmit power to a wireless power receiver includes a transmission coil to receive power from a power supply apparatus, and a transmission resonance unit to transmit the power received therein from the transmission coil to the wireless power receiver using resonance. The transmission resonance unit includes an inner loop, and an outer loop connected to the inner loop while surrounding the inner loop.

Abstract: At least one example embodiment discloses a semiconductor device including a direct memory access (DMA) system configured to directly access a memory to write first data to an address of the memory, wherein the DMA system includes an initializer configured to set a data transfer parameter for writing the first data to the memory during a flushing period of second data from a cache to the address by a processor, a creator configured to create the first data based on the set data transfer parameter, and a transferer configured to write the first data to the address of the memory after the flushing period based on the data transfer parameter.

Abstract: A method of operating a host controller interface includes receiving a buffer descriptor including sector information from a main memory, fetching data by using a source address included in the buffer descriptor, selecting one of a plurality of entries included in a security policy table by using the sector information, and determining whether to encrypt the fetched data by using a security policy included in the selected entry.

Abstract: A 3-dimensional image display device and a driving method thereof, the method including using a first array of a matrix of unit pixels to form an image while a remaining array of the unit pixels displays black, and forming openings in a barrier panel to expose the unit pixels of the first array, the width of the openings ranging from 1.5 to 2 times the width of the exposed unit pixels.

Abstract: The present invention relates to a near-field wireless power transfer system capable of having a constant efficiency regardless of a charging position of a receiver by only using a simple impedance matching circuit without using a separate existing complex adaptive impedance matching circuit or control circuit, and simultaneously transmitting power without having difficulty with impedance matching even for wireless power transmission to a plurality of electronic devices by applying a structure having a uniform mutual inductance between a wireless power transmitter and receiver.

Abstract: A method of operating a host controller interface includes receiving a buffer descriptor including sector information from a main memory, fetching data by using a source address included in the buffer descriptor, selecting one of a plurality of entries included in a security policy table by using the sector information, and determining whether to encrypt the fetched data by using a security policy included in the selected entry.

Abstract: An image control panel for a display device includes a first substrate and a second substrate facing each other, a lens electrode formed on the first substrate, a common electrode formed on the second substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. The common electrode includes a first common electrode and a second common electrode separated from each other.

Abstract: Provided is bearing steel having excellent fatigue life by minimizing segregation during casting of the bearing steel and reducing the generation of large carbides in a segregation band. The high-carbon chromium bearing steel includes 0.5 wt % to 1.2 wt % of carbon (C), 0.15 wt % to 2.0 wt % of silicon (Si), 0.05 wt % to 0.45 wt % of manganese (Mn), 0.025 wt % or less (excluding 0 wt %) of phosphorus (P), 0.025 wt % or less (excluding 0 wt %) of sulfur (S), 0.1 wt % to 1.6 wt % of chromium (Cr), 0.01 wt % to 0.3 wt % of Ce, and iron (Fe) as well as other unavoidable impurities as a remainder. A method of manufacturing the steel is also provided.

Abstract: A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal.

Abstract: A display device includes a display panel configured to receive a first-frame image signal for displaying a first-frame image in a first frame. The display panel is further configured to receive a second-frame image signal for displaying a second-frame image in a second frame that immediately follows the first frame such that the display panel appears to display a transition region associated with a boundary between a portion of the first-frame image and a portion of the second-frame image and moving in a moving direction. The display device further includes an optical effect layer and electrode sets. The electrode sets respectively overlap different portions of the optical effect layer and are configured for sequentially starting affecting the different portions of the optical effect layer such that the optical effect layer appears to display a light-blocking section that moves in the moving direction and overlaps the transition region.

Abstract: A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal.

Abstract: A display device includes a display panel configured to receive a first-frame image signal for displaying a first-frame image in a first frame. The display panel is further configured to receive a second-frame image signal for displaying a second-frame image in a second frame that immediately follows the first frame such that the display panel appears to display a transition region associated with a boudary between a portion of the first-frame image and a portion of the second-frame image and moving in a moving direction. The display device further includes an optical effect layer and electrode sets. The electrode sets respectively overlap different portions of the optical effect layer and are configured for sequentially starting affecting the different portions of the optical effect layer such that the optical effect layer appears to display a light-blocking section that moves in the moving direction and overlaps the transition region.

Abstract: A display device includes a display panel configured to receive a first-frame image signal for displaying a first-frame image in a first frame. The display panel is further configured to receive a second-frame image signal for displaying a second-frame image in a second frame that immediately follows the first frame such that the display panel appears to display a transition region associated with a boudary between a portion of the first-frame image and a portion of the second-frame image and moving in a moving direction. The display device further includes an optical effect layer and electrode sets. The electrode sets respectively overlap different portions of the optical effect layer and are configured for sequentially starting affecting the different portions of the optical effect layer such that the optical effect layer appears to display a light-blocking section that moves in the moving direction and overlaps the transition region.

Abstract: A system on chip (SoC) includes a central processing unit (CPU), an intellectual property (IP) block, and a memory management unit (MMU). The CPU is configured to set a prefetch direction corresponding to a working set of data. The IP block is configured to process the working set of data. The MMU is configured to prefetch a next page table entry from a page table based on the prefetch direction during address translation between a virtual address of the working set of data and a physical address.

Abstract: A method of operating an integrated circuit is provided. The method includes receiving a data block offset from a second storage device, obtaining a target entry address using the data block offset, and reading an entry among a plurality of entries comprised in a buffer descriptor stored in a first storage device based on the target entry address. The method also includes reading data from a data buffer among a plurality of data buffers included in the first storage device using a physical address included in the entry and transmitting the data to the second storage device.

Abstract: A system on chip (SoC) including a memory management unit (MMU) and a memory address translation method thereof are provided. The SoC includes a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets; an MMU module comprising a plurality of MMUs, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request, on which address translation has been performed in at least one of the MMUs, to the memory device; and a second bus interconnect configured to connect the master IP with the MMU module and to allocate one of the MMUs for each of the working sets.