Abstract: A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric formed between an elevated source and an elevated drain and surrounding a metal gate, and performing a chemical mechanical planarization (CMP) process on an upper surface of the elevated source, and in which a height of the metal gate becomes lower than a height of the elevated source according to the CMP process.

Abstract: A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric formed between an elevated source and an elevated drain and surrounding a metal gate, and performing a chemical mechanical planarization (CMP) process on an upper surface of the elevated source, and in which a height of the metal gate becomes lower than a height of the elevated source according to the CMP process.

Abstract: A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.

Abstract: A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric formed between an elevated source and an elevated drain and surrounding a metal gate, and performing a chemical mechanical planarization (CMP) process on an upper surface of the elevated source, and in which a height of the metal gate becomes lower than a height of the elevated source according to the CMP process.

Abstract: A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.

Abstract: A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric formed between an elevated source and an elevated drain and surrounding a metal gate, and performing a chemical mechanical planarization (CMP) process on an upper surface of the elevated source, and in which a height of the metal gate becomes lower than a height of the elevated source according to the CMP process.

Abstract: A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric formed between an elevated source and an elevated drain and surrounding a metal gate, and performing a chemical mechanical planarization (CMP) process on an upper surface of the elevated source, and in which a height of the metal gate becomes lower than a height of the elevated source according to the CMP process.

Abstract: In a method, a dummy gate layer structure and a mask layer are formed on a substrate. The mask layer is patterned to form masks. Spacers are formed on sidewalls of the mask. A dummy gate mask is formed between the spacers. The dummy gate layer structure is patterned using the dummy gate mask to form dummy gate structures. The dummy gate structure is replaced with a gate structure. When the mask is formed, an initial layout of masks extending in a first direction is designed. An offset bias in a second direction is provided for a specific region of the initial layout to design a final layout having a width in the second direction varying along the first direction. The mask layer is patterned according to the final layout to form the masks having a width varying along the first direction.

Abstract: In a method, a dummy gate layer structure and a mask layer are formed on a substrate. The mask layer is patterned to form masks. Spacers are formed on sidewalls of the mask. A dummy gate mask is formed between the spacers. The dummy gate layer structure is patterned using the dummy gate mask to form dummy gate structures. The dummy gate structure is replaced with a gate structure. When the mask is formed, an initial layout of masks extending in a first direction is designed. An offset bias in a second direction is provided for a specific region of the initial layout to design a final layout having a width in the second direction varying along the first direction. The mask layer is patterned according to the final layout to form the masks having a width varying along the first direction.

Abstract: A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric formed between an elevated source and an elevated drain and surrounding a metal gate, and performing a chemical mechanical planarization (CMP) process on an upper surface of the elevated source, and in which a height of the metal gate becomes lower than a height of the elevated source according to the CMP process.

Abstract: Oligomers of polyarylene polyethethers (PAPE) having a mol wt Mn in the range from 1000 to about 10,000 are converted to monofunctionalized macromers, so as, in the first instance, to provide a reactive double bond (for example, a vinylbenzyl group) at only one end of the PAPE; and, in the second instance, to provide a triple bond (benzylethynyl group) at only one end of the PAPE. The macromer may be a polysulfone, a polyketone, or a copolymer containing both sulfone and ketone-containing units; or, the macromer may be monofunctionalized PPO. The synthesis of macromers with terminal double bonds is carried out with a fast and quantitative modified Williamson etherification of the PAPE with an electrophilic haloalkyl reactant ("HAR") such as chloromethylstyrene ("C1MS") in the presence of a major molar amount (more than 50 mol % based on the number of moles of OH group originally present in the oligomer) of a phase transfer catalyst such as tetrabutylammonium hydrogen sulfate ("TBAH").