Patents by Inventor Kwan Jai Lee
Kwan Jai Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160162091Abstract: A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.Type: ApplicationFiled: February 10, 2016Publication date: June 9, 2016Inventors: JEONG-KYU HA, KWAN-JAi LEE, JAE-MIN JUNG, KYONG-SOON CHO, NA-RAE SHIN, KYOUNG-SUK YANG, PA-LAN LEE, SO-YOUNG LIM
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Patent number: 9280182Abstract: A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.Type: GrantFiled: March 3, 2014Date of Patent: March 8, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong-Kyu Ha, Kwan-Jai Lee, Jae-Min Jung, Kyong-Soon Cho, Na-Rae Shin, Kyoung-Suk Yang, Pa-Lan Lee, So-Young Lim
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Patent number: 9113545Abstract: A tape wiring substrate includes a base film having at least one recess in a first surface of the base film and a chip-mounting region on which a semiconductor chip is included on a second surface of the base film. A wiring pattern is formed on the second surface of the base film and is extended to an edge of the chip-mounting region. A protection film covers the wiring pattern.Type: GrantFiled: September 5, 2012Date of Patent: August 18, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-uk Han, Young-shin Kwon, Kwan-jai Lee, Jae-min Jung, Kyong-soon Cho, Jeong-kyu Ha
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Patent number: 9059162Abstract: A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film.Type: GrantFiled: July 2, 2013Date of Patent: June 16, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Kyu Ha, Kwan-Jai Lee, Jae-Min Jung, Kyong-Soon Cho, Na-Rae Shin, Kyoung-Suk Yang, Pa-Lan Lee, So-Young Lim
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Patent number: 8853694Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.Type: GrantFiled: November 5, 2012Date of Patent: October 7, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Uk Han, Jeong-Kyu Ha, Young-Shin Kwon, Seung-Hwan Kim, Kwan-Jai Lee
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Publication number: 20140246687Abstract: A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.Type: ApplicationFiled: March 3, 2014Publication date: September 4, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong-Kyu Ha, Kwan-Jai Lee, Jae-Min Jung, Kyong-Soon Cho, Na-Rae Shin, Kyoung-Suk Yang, Pa-Lan Lee, So-Young Lim
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Patent number: 8803301Abstract: A semiconductor package may include a substrate, a semiconductor chip disposed on the substrate, a communication terminal and a static electricity inducing terminal connected to a ground. The package may include a first sealant that comprises a voltage sensitive material and that covers the semiconductor chip and a static electricity blocking layer that provides a conductive pathway from the first sealant to only the static electric inducing terminal. The static electricity blocking layer may prevent the communication terminal from being electrically connected to the first sealant. If a buildup of charge is applied to the device, the first sealant may become polarized and/or conductive. The extra voltage may travel through the first sealant to the static electricity inducing terminal via an opening in the static electricity blocking layer. The semiconductor chip and the communication terminal may not be affected by the extra charge.Type: GrantFiled: March 22, 2012Date of Patent: August 12, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kyong-soon Cho, Seung-kon Mok, Kwan-jai Lee, Jae-min Jung
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Publication number: 20140054793Abstract: A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film.Type: ApplicationFiled: July 2, 2013Publication date: February 27, 2014Inventors: Jeong-Kyu Ha, Kwan-Jai Lee, Jae-Min Jung, Kyong-Soon Cho, Na-Rae Shin, Kyoung-Suk Yang, Pa-Lan Lee, So-Young Lim
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Patent number: 8629547Abstract: A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.Type: GrantFiled: July 13, 2011Date of Patent: January 14, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kyong-Soon Cho, Chang-Su Kim, Kwan-Jai Lee, Kyoung-Sei Choi, Jae-Hyok Ko, Keung-Beum Kim
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Publication number: 20130148312Abstract: A tape wiring substrate includes a base film having at least one recess in a first surface of the base film and a chip-mounting region on which a semiconductor chip is included on a second surface of the base film. A wiring pattern is formed on the second surface of the base film and is extended to an edge of the chip-mounting region. A protection film covers the wiring pattern.Type: ApplicationFiled: September 5, 2012Publication date: June 13, 2013Inventors: Sang-Uk Han, Young-Shin Kwon, Kwan-Jai Lee, Jae-Min Jung, Kyong-Soon Cho, Jeong-Kyu Ha
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Publication number: 20120274868Abstract: A semiconductor package may include a substrate, a semiconductor chip disposed on the substrate, a communication terminal and a static electricity inducing terminal connected to a ground. The package may include a first sealant that comprises a voltage sensitive material and that covers the semiconductor chip and a static electricity blocking layer that provides a conductive pathway from the first sealant to only the static electric inducing terminal. The static electricity blocking layer may prevent the communication terminal from being electrically connected to the first sealant. If a buildup of charge is applied to the device, the first sealant may become polarized and/or conductive. The extra voltage may travel through the first sealant to the static electricity inducing terminal via an opening in the static electricity blocking layer. The semiconductor chip and the communication terminal may not be affected by the extra charge.Type: ApplicationFiled: March 22, 2012Publication date: November 1, 2012Inventors: Kyong-soon Cho, Seung-kon Mok, Kwan-jai Lee, Jae-min Jung
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Publication number: 20120074540Abstract: A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.Type: ApplicationFiled: July 13, 2011Publication date: March 29, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyong-Soon CHO, Chang-Su KIM, Kwan-Jai LEE, Kyoung-Sei CHOI, Jae-Hyok KO, Keung-Beum Kim
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Publication number: 20120021600Abstract: A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area.Type: ApplicationFiled: July 18, 2011Publication date: January 26, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-Uk Han, Dae-Woo Son, Kwan-Jai Lee, Ye-Chung Chung, Jeong-Kyu Ha, Yun-Young Kim
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Patent number: 7339262Abstract: A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply voltage. The tape circuit substrate may include an insulation film and a wiring pattern formed on the insulation film to define an electronic device-mounting region and including a ground electrode. The tape circuit substrate may include a ground electrode pattern formed at the electronic device-mounting region so as to be insulated from the wiring pattern, except where the ground electrode pattern is connected to the ground electrode.Type: GrantFiled: July 28, 2004Date of Patent: March 4, 2008Assignee: Samsung Electronics Co., LtdInventors: Dae-Woo Son, Sa-Yoon Kang, Kwan-Jai Lee
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Patent number: 7247936Abstract: A semiconductor chip package includes an IC chip and a tape circuit substrate. The tape circuit substrate has a base film and a plurality of beam leads formed on the base film. One end portion of each beam lead extends from the base film, and the extended portion has a widthwise wavy portion. The widthwise wavy portion may be, for example, semicircular shaped, S-shaped or zig-zag shaped. The IC chip has chip pads formed on a top surface thereof.Type: GrantFiled: December 17, 2003Date of Patent: July 24, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Woo Son, Jin-Hyuk Lee, Kwan-Jai Lee
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Publication number: 20050093114Abstract: A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply voltage. The tape circuit substrate may include an insulation film and a wiring pattern formed on the insulation film to define an electronic device-mounting region and including a ground electrode. The tape circuit substrate may include a ground electrode pattern formed at the electronic device-mounting region so as to be insulated from the wiring pattern, except where the ground electrode pattern is connected to the ground electrode.Type: ApplicationFiled: July 28, 2004Publication date: May 5, 2005Inventors: Dae-Woo Son, Sa-Yoon Kang, Kwan-Jai Lee
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Patent number: 6878570Abstract: There are disclosed a stacked package formed by stacking semiconductor device packages and a manufacturing method thereof. Each package includes leads and connection terminals. A semiconductor chip is electrically connected to the connection terminals. A package body has the same thickness as that of the lead so as to expose the upper and the lower surfaces of the leads to the package body. Each of the packages is stacked on another package by electrically connecting the exposed upper and lower surfaces of the leads with each other. The manufacturing method has preparing lead frames, attaching an adhesive tape to the lower surface of the lead frame, bonding a semiconductor chip to the adhesive tape in the chip receiving cavity between the leads, connecting the semiconductor chip to the connection terminals, forming a package body, removing the adhesive tape; removing dam bars from the side frame, separating packages from the lead frame, and forming a stacked package by stacking a plurality of the packages.Type: GrantFiled: July 29, 2004Date of Patent: April 12, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Ju Hyun Lyu, Kwan Jai Lee, Tae Je Cho
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Patent number: 6849949Abstract: A stacked package formed by stacking semiconductor device packages and a method of manufacturing a stacked semiconductor package. Each package includes leads and connection terminals. A semiconductor chip is electrically connected to the connection terminals. A package body has the same thickness as that of the lead so as to expose the upper and the lower surfaces of the leads at a surface of the package body. Each of the packages is stacked on another package by electrically connecting the exposed surfaces of the leads. The manufacturing method includes preparing lead frames, including a plurality of leads, supporting a semiconductor chip in a chip receiving cavity between the leads, connecting the semiconductor chip to the connection terminals of the leads, forming a package body of a thickness such that a portion of surface of the leads are exposed, separating packages from the lead frame, and forming a stacked package by stacking a plurality of the packages.Type: GrantFiled: March 23, 2000Date of Patent: February 1, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Ju Hyun Lyu, Kwan Jai Lee, Tae Je Cho
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Publication number: 20040263667Abstract: PURPOSE: A semiconductor package and a method for fabricating the same are provided to shorten a length of a signal line for connecting a semiconductor chip with a substrate and simplify a structure of the semiconductor package.Type: ApplicationFiled: May 12, 2004Publication date: December 30, 2004Inventors: Kwan-Jai Lee, Sa-Yoon Kang, Seung-Kon Mok
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Publication number: 20040178501Abstract: A semiconductor chip package includes an IC chip and a tape circuit substrate. The tape circuit substrate has a base film and a plurality of beam leads formed on the base film. One end portion of each beam lead extends from the base film, and the extended portion has a wavy portion. The wavy portion can be, for example, semicircular shaped, an S-shaped, or a zigzag shaped. The IC chip has chip pads formed on a top surface thereof. The beam lead is bonded to the chip pad through an inner lead bonding (ILB) process. During the ILB process, the wavy portion disperses the stress produced in the beam lead. Therefore, a crack or a break of the beam lead due to the stress can be effectively prevented, improving interconnection reliability between the IC chip and the tape circuit substrate.Type: ApplicationFiled: December 17, 2003Publication date: September 16, 2004Inventors: Dae-Woo Son, Jin-Hyuk Lee, Kwan-Jai Lee