Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness.

Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness.

Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness.