Patents by Inventor Kwan-Jong Roh
Kwan-Jong Roh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8008177Abstract: A method for fabricating a semiconductor device is provided using a nickel salicide process. The method includes forming a gate pattern and a source/drain region on a silicon substrate, forming a Ni-based metal layer for silicide on the silicon substrate where the gate pattern and the source/drain region are formed, and forming an N-rich titanium nitride layer on the Ni-based metal layer for silicide. Next, a thermal treatment is applied to the silicon substrate where the Ni-based metal layer for silicide and the N-rich titanium nitride layer are formed, thereby forming a nickel silicide on each of the gate pattern and the source/drain region. Then, the Ni-based metal layer for silicide and the N-rich titanium nitride layer are selectively removed to expose a top portion of a nickel silicide layer formed on the gate pattern and the source/drain region.Type: GrantFiled: July 17, 2003Date of Patent: August 30, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Min-chul San, Ja-hum Ku, Chul-sung Kim, Kwan-jong Roh, Min-joo Kim
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Patent number: 7932149Abstract: In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.Type: GrantFiled: May 19, 2009Date of Patent: April 26, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hyun Park, Jeong-Uk Han, Jae-Min Yu, Young-Cheon Jeong, Sang-Hoon Park, Kwan-Jong Roh, Byeong-Cheol Lim, Yong-Seok Chung
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Patent number: 7781322Abstract: Provided are exemplary methods for forming a nickel silicide layer and semiconductor devices incorporating a nickel silicide layer that provides increased stability for subsequent processing at temperatures above 450° C. In particular, the nickel silicide layer is formed from a nickel alloy having a minor portion of an alloying metal, such as tantalum, and exhibits reduced agglomeration and retarded the phase transition between NiSi and NiSi2 to suppress increases in the sheet resistance and improve the utility for use with fine patterns. As formed, the nickel silicide layer includes both a lower layer consisting primarily of nickel and silicon and a thinner upper layer that incorporates the majority of the alloying metal.Type: GrantFiled: December 4, 2003Date of Patent: August 24, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Ja-Hum Ku, Kwan-Jong Roh, Min-Chul Sun, Min-Joo Kim
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Patent number: 7709340Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.Type: GrantFiled: February 12, 2007Date of Patent: May 4, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-hyon Ahn, Jae-cheol Yoo, Ki-seog Youn, Kwan-jong Roh, Su-gon Bae, Ki-young Kim
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Publication number: 20090286369Abstract: In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.Type: ApplicationFiled: May 19, 2009Publication date: November 19, 2009Inventors: Jee-Hyun Park, Jeong-Uk Han, Jae-Min Yu, Young-Cheon Jeong, Sang-Hoon Park, Kwan-Jong Roh, Byeong-Cheol Lim, Yong-Seok Chung
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Patent number: 7569483Abstract: Methods of forming metal silicide layers include a convection-based annealing step to convert a metal layer into a metal silicide layer. These methods may include forming a silicon layer on a substrate and forming a metal layer (e.g., nickel layer) in direct contact with the silicon layer. A step is then performed to convert at least a portion of the metal layer into a metal silicide layer. This conversion step is includes exposing the metal layer to an inert heat transferring gas (e.g., argon, nitrogen) in a convection or conduction apparatus.Type: GrantFiled: August 8, 2005Date of Patent: August 4, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sug-Woo Jung, Gil-Heyun Choi, Jong-Ho Yun, Kwan-Jong Roh, Eun-Ji Jung, Hyun-Su Kim
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Patent number: 7557415Abstract: A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate, a nitride liner formed on the first oxide film, a second oxide film formed in contact with the upper end of the first oxide film and on the exposed corner portion and an upper surface of the semiconductor substrate, a field insulating film formed on the nitride liner to substantially fill the trench, and a field protecting film formed in contact with the second oxide film and filling a trench edge recess formed between the field insulating film and the second oxide film.Type: GrantFiled: January 8, 2007Date of Patent: July 7, 2009Assignee: Samsung Electroncis Co., Ltd.Inventors: Ki-seog Youn, Jong-hyon Ahn, Kwan-jong Roh, Hye-kyoung Lee
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Patent number: 7375025Abstract: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.Type: GrantFiled: November 16, 2005Date of Patent: May 20, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Eung-Joon Lee, In-Sun Park, Kwan-Jong Roh
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Publication number: 20070187770Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.Type: ApplicationFiled: February 12, 2007Publication date: August 16, 2007Inventors: Jong-hyon Ahn, Jae-cheol Yoo, Ki-seog Youn, Kwan-jong Roh, Su-gon Bae, Ki-young Kim
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Publication number: 20070164391Abstract: A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate, a nitride liner formed on the first oxide film, a second oxide film formed in contact with the upper end of the first oxide film and on the exposed corner portion and an upper surface of the semiconductor substrate, a field insulating film formed on the nitride liner to substantially fill the trench, and a field protecting film formed in contact with the second oxide film and filling a trench edge recess formed between the field insulating film and the second oxide film.Type: ApplicationFiled: January 8, 2007Publication date: July 19, 2007Inventors: Ki-seog Youn, Jong-hyon Ahn, Kwan-Jong Roh, Hye-Kyoung Lee
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Patent number: 7232756Abstract: Provided are exemplary methods for forming a semiconductor devices incorporating silicide layers formed at temperatures below about 700° C., such as nickel silicides, that are formed after completion of a silicide blocking layer (SBL). The formation of the SBL tends to deactivate dopant species in the gate, lightly-doped drain and/or source/drain regions. The exemplary methods include a post-SBL activation anneal either in place of or in addition to the traditional post-implant activation anneal. The use of the post-SBL anneal produces CMOS transistors having properties that reflect reactivation of sufficient dopant to overcome the SBL process effects, while allowing the use of lower temperature silicides, including nickel silicides and, in particular, nickel silicides incorporating a minor portion of an alloying metal, such as tantalum, the exhibits reduced agglomeration and improved temperature stability.Type: GrantFiled: March 30, 2004Date of Patent: June 19, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Ja-Hum Ku, Kwan-Jong Roh, Min-Chul Sun, Min-Joo Kim, Sug-Woo Jung, Sun-Pil Youn
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Publication number: 20060223296Abstract: A semiconductor device having a self-aligned silicide layer and a method thereof are provided. The device includes a device isolation layer formed on the substrate to define an active region and a gate pattern crossing over the active region. A spacer insulating layer is formed on both sidewalls of the gate pattern. First and second salicide layers are formed on an upper portion of the gate pattern, and the first salicide layer is formed on the active region between the spacer insulating layer and the device isolation layer. The first and the second salicide layers on the gate pattern are alternately formed to be connected with each other. The first salicide layer is agglomeratedly formed on a narrow gate pattern, and the second salicide layer is formed within interrupted portions of the first salicide layer, thereby forming a patched salicide layer.Type: ApplicationFiled: July 13, 2005Publication date: October 5, 2006Inventors: Min-Chul Sun, Ja-Hum Ku, Sug-Woo Jung, Sung-Kee Han, Min-Joo Kim, Kwan-Jong Roh
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Patent number: 7084061Abstract: Methods of fabricating a semiconductor device having a MOS transistor with a strained channel are provided. The method includes forming a MOS transistor at a portion of a semiconductor substrate. The MOS transistor is formed to have source/drain regions spaced apart from each other and a gate electrode located over a channel region between the source/drain regions. A stress layer is formed on the semiconductor substrate having the MOS transistor. The stress layer is then annealed to convert a physical stress of the stress layer into a tensile stress or increase a tensile stress of the stress layer.Type: GrantFiled: March 12, 2004Date of Patent: August 1, 2006Assignee: Samsung Electronics, Co., Ltd.Inventors: Min-Chul Sun, Ja-Hum Ku, Sug-Woo Jung, Sun-Pil Youn, Min-Joo Kim, Kwan-Jong Roh
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Publication number: 20060068585Abstract: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.Type: ApplicationFiled: November 16, 2005Publication date: March 30, 2006Inventors: Eung-Joon Lee, In-Sun Park, Kwan-Jong Roh
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Publication number: 20060063380Abstract: Methods of forming metal silicide layers include a convection-based annealing step to convert a metal layer into a metal silicide layer. These methods may include forming a silicon layer on a substrate and forming a metal layer (e.g., nickel layer) in direct contact with the silicon layer. A step is then performed to convert at least a portion of the metal layer into a metal silicide layer. This conversion step is includes exposing the metal layer to an inert heat transferring gas (e.g., argon, nitrogen) in a convection or conduction apparatus.Type: ApplicationFiled: August 8, 2005Publication date: March 23, 2006Inventors: Sug-Woo Jung, Gil-Heyun Choi, Jong-Ho Yun, Kwan-Jong Roh, Eun-Ji Jung, Hyun-Su Kim
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Patent number: 7005373Abstract: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.Type: GrantFiled: March 2, 2004Date of Patent: February 28, 2006Assignee: Samsung Electronics, Co., Ltd.Inventors: Eung-Joon Lee, In-Sun Park, Kwan-Jong Roh
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Publication number: 20060003534Abstract: A salicide process using a bi-metal layer and method of fabricating a semiconductor substrate using the same are disclosed herein. The salicide process includes forming a main metal layer on a semiconductor substrate containing silicon. A main metal alloy layer containing at least one species of alloy element is formed on the main metal layer. The semiconductor substrate having the main metal layer and the main metal alloy layer is annealed to form a main metal alloy silicide layer. According to an exemplary embodiment of the present invention, the main metal layer may be formed of a nickel (Ni) layer, and the main metal alloy layer may be formed of a nickel tantalum alloy layer. In this case, a nickel tantalum silicide layer having improved thermal stability and electrical characteristics are formed.Type: ApplicationFiled: June 8, 2005Publication date: January 5, 2006Inventors: Kwan-Jong Roh, Min-Chul Sun, Ja-Hum Ku, Sug-Woo Jung, Min-Joo Kim, Sung-Kee Han
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Publication number: 20050236715Abstract: Provided are exemplary methods for forming a nickel silicide layer and semiconductor devices incorporating a nickel silicide layer that provides increased stability for subsequent processing at temperatures above 450° C. In particular, the nickel silicide layer is formed from a nickel alloy having a minor portion of an alloying metal, such as tantalum, and exhibits reduced agglomeration and retarded the phase transition between NiSi and NiSi2 to suppress increases in the sheet resistance and improve the utility for use with fine patterns. As formed, the nickel silicide layer includes both a lower layer consisting primarily of nickel and silicon and a thinner upper layer that incorporates the majority of the alloying metal.Type: ApplicationFiled: June 9, 2005Publication date: October 27, 2005Inventors: Ja-Hum Ku, Kwan-Jong Roh, Min-Chul Sun, Min-Joo Kim
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Publication number: 20050158996Abstract: A nickel salicide process includes preparing a substrate having a silicon region and an insulating region containing silicon. Nickel is deposited on the substrate, and the nickel is annealed at a first temperature of 300° C. to 380° C. to selectively form a mono-nickel mono-silicide layer on the silicon region and to leave an unreacted nickel layer on the insulating region. The unreacted nickel layer is selectively removed to expose the insulating region and to leave the mono-nickel mono-silicide layer on the silicon region. Subsequently, the mono-nickel mono-silicide layer is annealed at a second temperature which is higher than the first temperature to form a thermally stable mono-nickel mono-silicide layer and without a phase transition of the mono-nickel mono-silicide layer.Type: ApplicationFiled: November 16, 2004Publication date: July 21, 2005Inventors: Min-Joo Kim, Ja-Hum Ku, Min-Chul Sun, Kwan-Jong Roh
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Publication number: 20040266182Abstract: Provided are exemplary methods for forming a nickel silicide layer and semiconductor devices incorporating a nickel silicide layer that provides increased stability for subsequent processing at temperatures above 450° C. In particular, the nickel silicide layer is formed from a nickel alloy having a minor portion of an alloying metal, such as tantalum, and exhibits reduced agglomeration and retarded the phase transition between NiSi and NiSi2 to suppress increases in the sheet resistance and improve the utility for use with fine patterns. As formed, the nickel silicide layer includes both a lower layer consisting primarily of nickel and silicon and a thinner upper layer that incorporates the majority of the alloying metal.Type: ApplicationFiled: December 4, 2003Publication date: December 30, 2004Inventors: Ja-Hum Ku, Kwan-Jong Roh, Min-Chul Sun, Min-Joo Kim