Abstract: An array substrate for a liquid crystal display device can include a plurality of gate lines arranged in one direction to correspond to an active area on a substrate; a plurality of data lines configured to cross the plurality of gate lines in a perpendicular direction; a plurality of pixel electrodes respectively positioned at intersections between the plurality of gate lines and the plurality of data lines; and a plurality of data link lines respectively connected to a (4n?2)th data line in the active area and a (4n?2)th data pad in the non-active area, and a (4n?1)th data line in the active area and a (4n?1)th data pad in the non-active area, where n is a natural number, in which at least some of the plurality of data link lines are located at a different layer level than the plurality of data lines.

Abstract: An array substrate for a liquid crystal display device can include a plurality of gate lines arranged in one direction to correspond to an active area on a substrate; a plurality of data lines configured to cross the plurality of gate lines in a perpendicular direction; a plurality of pixel electrodes respectively positioned at intersections between the plurality of gate lines and the plurality of data lines; and a plurality of data link lines respectively connected to a (4n-2)th data line in the active area and a (4n-2)th data pad in the non-active area, and a (4n-1)th data line in the active area and a (4n-1)th data pad in the non-active area, where n is a natural number, in which at least some of the plurality of data link lines are located at a different layer level than the plurality of data lines.

Abstract: A method comprises receiving a digital television signal including a system time table providing a current date and time of day information and an event information table containing information for events on defined virtual channels; demultiplexing the system time table and the event information table from the digital television signal; parsing current event information from the demultiplexed system time table, the current event information defining at least one of a source identification and event identification for a current event; parsing time information of a corresponding event from the demultiplexed event information table; and updating the time information of the event according to the parsed current event information.

Abstract: An impulse radio-based ultra wideband communication system, using an ultra wideband impulse and a 1-bit high-speed digital sampler, includes a transmitting RF module, a receiving RF module, a signal recovery unit, a transmitting signal processor, a receiving signal processor, and an ultra wideband antenna. The transmitting RF module includes an integrated impulse generator capable of implementing on-off-keying modulation and pulse position modulation, and an amplifier for amplifying output of the integrated impulse generator. The receiving RF module includes a two stage envelope detector for detecting a received signal and a comparator for converting the detected signal into a rectangular pulse. The signal recovery unit restores the signal from the receiving RF module to a digital signal using the 1-bit digital sampler. The signal processor includes a receiving signal processor for synchronizing the digital signal and decoding the detected signal.

Abstract: A laser diode drive circuit drives a high-power laser diode using a single voltage source and a transistor. The laser diode drive circuit includes: a voltage-level shifter shifting an output voltage of an analog signal processor to a predetermined-level voltage; a voltage adder for adding a predetermined voltage according to a record or reproduction mode of an optical disc to the level-shifted voltage; and an amplifier for amplifying a current signal of a power-supply unit in response to the added voltage and outputting the amplified current signal to a laser diode.

Abstract: Disclosed herein are novel binaphthol derivatives and methods for the optical resolution of amino acids or amino alcohols and for the optical transformation of D, L-forms of amino acids using the same.

Abstract: Disclosed is an internal voltage generator, which includes a detecting means for detecting a level of an internal voltage, an oscillator for generating a driving pulse signal in response to an output signal of the detecting means, a first driving unit for outputting a first pulse signal after receiving the driving pulse signal, a second driving unit for outputting a second pulse signal after receiving the driving pulse signal, and a pumping unit for changing a potential level of the internal voltage after selectively receiving one of the first pulse signal and the second pulse signal.

Abstract: An organic electro luminescence device includes: a display region and a non-display region defined in first and second substrates, sub-pixels defined in the display region; an array element including at least one TFT in the display region of the first substrate in each sub-pixel; a first electrode in an inner surface of the second substrate; a buffer in a predetermined region to partition an emission region of each sub-pixel on the first electrode, and an electrode separator on the buffer; an insulating layer in the emission region of each sub-pixel, and a spacer formed on the insulating layer; an organic electro luminescent layer in the emission region of each sub-pixel, the emission region including the insulating layer and the spacer; and a second electrode on the second substrate where the organic electro luminescent layer is formed.

Abstract: A transmission power detecting apparatus of a CDMA system is disclosed by which since the power detection of the RF CDMA signal is digitally performed and no RF device (an RSSI detector) which is sensitive to a temperature change is used, a power of the RF CDMA signal can be more accurately detected. In addition, since an IF analog CDMA signal to be measure is sampled and then an average power of the sampled digital IF CDMA signal is obtained, accuracy in power detection and transmission power adjustment can be accomplished. Moreover, since the power of the baseband digital CDMA signal containing a traffic is detected to provide a reference value for adjusting the power of the RF CDMA signal, an error generated in determining a power of the RF CDMA signal as in the conventional art can be reduced.

Abstract: Disclosed is an organic electro luminescence device having a display area and a dummy area, the display area having a plurality of display pixels for displaying an image, and the dummy area having a plurality of dummy pixels and being provided at a periphery of the display area, an anode at the display area on a substrate; a buffer layer on the anode of the display area and on the substrate of the dummy area; a barrier on the buffer layer for partitioning the display pixels and the dummy pixels on the substrate and; an organic electro luminescence layer in the display and dummy pixels.

Abstract: Provided is directed to a circuit for controlling data and a data strobe driver in a semiconductor memory device, including: a first delay unit for outputting a data signal with a variable delay; a DQ driver for outputting a data signal according to the data signal passed through the first delay unit and a driver select signal; a second delay unit for outputting a data strobe signal with a variable delay; and a DQS driver for outputting the data strobe signal passed through the second delay unit by being driven according to the driver select signal.

Abstract: An organic electroluminescent device includes first and second substrates attached by a seal pattern, array elements including a plurality of thin film transistors formed on the first substrate, a first electrode formed on a rear surface of the second substrate, a plurality of electrode separators formed on the rear surface of the first electrode, wherein the plurality of electrode separators is made of an insulating material defining sub-pixel regions that correspond to each thin film transistor, an organic electroluminescent layer formed on a rear surface of the first electrode in each of the sub-pixel regions, a second electrode formed on a rear surface of the organic electroluminescent layer in each of sub-pixel regions, a conductive connector formed between the first and second substrates in each sub-pixel region for connecting to the second electrode of a sub-pixel region.

Abstract: A high voltage supply circuit and method of supplying a high voltage are disclosed. A second pumping voltage-generating unit, in addition to a primary pumping voltage-generating unit for generating a pumping voltage, is provided. The second pumping voltage-generating unit is operated for a certain time simultaneously with the primary voltage-generating unit when a normal operating mode is switched to an auto-refresh operating mode where current consumption is abruptly increased in order to raise the pumping voltage higher than a target voltage. Therefore, the resulting pumping voltage is prevented from being lower below the target voltage even if the operating mode where current consumption is abruptly increased is entered, and the reliability of the circuit is therefore increased.

Abstract: Low-resistance gate transistor and method for fabricating the same, in which a metal sidewall is formed at sides of a gate poly-silicon layer to reduce the resistance and the height of a gate, thereby improving the characteristics of a semiconductor device, the low-resistance gate transistor of the present invention including a gate oxide film formed on a semiconductor substrate; a gate formed on the gate oxide film; a first gate sidewall having a vertical pattern in contact with a side of the gate at both sides of the gate and a horizontal pattern formed on the gate oxide film extended from the vertical pattern; second gate sidewalls formed of a material having a resistivity lower than the gate, each having one side in contact with the vertical pattern of the first gate sidewall and a bottom in contact with the horizontal pattern of the first gate sidewall with a round surface; an insulating layer formed on an entire surface including the gate and the first and second gate sidewalls; and, source/drain region

Abstract: The present invention relates to a DRAM cell array and a fabrication method thereof, and which includes: a semiconductor substrate on which a plurality of active regions and isolation regions in a rectangular strip shape at a predetermined distance from each other are defined; a plurality of transistors each having a gate electrode formed by interleaving a gate insulating film on the active regions and a source and drain region formed in the substrate at both sides of the gate electrodes; a plurality of capacitors connected to one of the source and drain regions, and having a lower electrode and a upper electrode formed by interleaving a capacitor insulating film on the lower electrode; a plurality of bit lines connected to one of the source and drain regions of the plurality of transistors; and a plurality of word lines comprised of first word lines and second word lines arranged in parallel which are vertical to the direction in which the bit lines are arranged, and selectively connect the gate electrodes o

Abstract: Low-resistance gate transistor and method for fabricating the same, in which a metal sidewall is formed at sides of a gate polysilicon layer to reduce the resistance and the height of a gate, thereby improving the characteristics of a semiconductor device, the low-resistance gate transistor of the present invention including a gate oxide film formed on a semiconductor substrate; a gate formed on the gate oxide film; a first gate sidewall having a vertical pattern in contact with a side of the gate at both sides of the gate and a horizontal pattern formed on the gate oxide film extended from the vertical pattern; second gate sidewalls formed of a material having a resistivity lower than the gate, each having one side in contact with the vertical pattern of the first gate sidewall and a bottom in contact with the horizontal pattern of the first gate sidewall with a round surface; an insulating layer formed on an entire surface including the gate and the first and second gate sidewalls; and, source/drain regions

Abstract: Low-resistance gate transistor and method for fabricating the same, in which a metal sidewall is formed at sides of a gate polysilicon layer to reduce the resistance and the height of a gate, thereby improving the characteristics of a semiconductor device, the low-resistance gate transistor of the present invention including a gate oxide film formed on a semiconductor substrate; a gate formed on the gate oxide film; a first gate sidewall having a vertical pattern in contact with a side of the gate at both sides of the gate and a horizontal pattern formed on the gate oxide film extended from the vertical pattern; second gate sidewalls formed of a material having a resistivity lower than the gate, each having one side in contact with the vertical pattern of the first gate sidewall and a bottom in contact with the horizontal pattern of the first gate sidewall with a round surface; an insulating layer formed on an entire surface including the gate and the first and second gate sidewalls; and, source/drain regions

Abstract: A transmission power detecting apparatus of a CDMA system is disclosed by which since the power detection of the RF CDMA signal is digitally performed and no RF device (an RSSI detector) which is sensitive to a temperature change is used, a power of the RF CDMA signal can be more accurately detected. In addition, since an IF analog CDMA signal to be measure is sampled and then an average power of the sampled digital IF CDMA signal is obtained, accuracy in power detection and transmission power adjustment can be accomplished. Moreover, since the power of the baseband digital CDMA signal containing a traffic is detected to provide a reference value for adjusting the power of the RF CDMA signal, an error generated in determining a power of the RF CDMA signal as in the conventional art can be reduced.

Abstract: The present invention relates to a DRAM cell array and a fabrication method thereof, and which includes: a semiconductor substrate on which a plurality of active regions and isolation regions in a rectangular strip shape at a predetermined distance from each other are defined; a plurality of transistors each having a gate electrode formed by interleaving a gate insulating film on the active regions and a source and drain region formed in the substrate at both sides of the gate electrodes; a plurality of capacitors connected to one of the source and drain regions, and having a lower electrode and a upper electrode formed by interleaving a capacitor insulating film on the lower electrode; a plurality of bit lines connected to one of the source and drain regions of the plurality of transistors; and a plurality of word lines comprised of first word lines and second word lines arranged in parallel which are vertical to the direction in which the bit lines are arranged, and selectively connect the gate electrodes o

Abstract: The present invention relates to a DRAM cell array and a fabrication method thereof, and which includes: a semiconductor substrate on which a plurality of active regions and isolation regions in a rectangular strip shape at a predetermined distance from each other are defined; a plurality of transistors each having a gate electrode formed by interleaving a gate insulating film on the active regions and a source and drain region formed in the substrate at both sides of the gate electrodes; a plurality of capacitors connected to one of the source and drain regions, and having a lower electrode and a upper electrode formed by interleaving a capacitor insulating film on the lower electrode; a plurality of bit lines connected to one of the source and drain regions of the plurality of transistors; and a plurality of word lines comprised of first word lines and second word lines arranged in parallel which are vertical to the direction in which the bit lines are arranged, and selectively connect the gate electrodes o