Abstract: A semiconductor device may include a cell chip and a core/peripheral chip on the cell chip. The cell chip may include a first semiconductor substrate, a first device layer disposed on the first semiconductor substrate, a bottom electrode disposed on the first device layer, a dielectric layer conformally covering a top surface of the first device layer and the bottom electrode, a top electrode disposed on the bottom electrode and spaced apart from the bottom electrode by the dielectric layer, an insulating layer provided on the first device layer to cover the top electrode, and a first contact vertically penetrating one of the first semiconductor substrate or the insulating layer and connected to the top electrode. The top electrode may include a semiconductor layer and a metal layer that are stacked, and the first contact may be in contact with the metal layer.

Abstract: Integrated circuit (IC) package substrate with an embedded trace substrate (ETS) layer on a substrate, and related fabrication methods. The package substrate of the IC package includes an ETS layer provided on the substrate to facilitate providing higher density substrate interconnects to provide bump/solder joints for coupling a semiconductor die to the package substrate. ETS interconnects in the ETS layer in the package substrate facilitates die connections having a reduced line-spacing ratio (L/S) (e.g., 5.0 micrometers (?m)/5.0 ?m or less) over substrate interconnects in a substrate. In additional exemplary aspects, raised metal pillar interconnects are formed in contact with respective ETS interconnects of the ETS layer of the package substrate to avoid or reduce metal consumption by die solder disposed on metal pillar interconnects of the ETS layer providing bump/solder joints.

Abstract: A thermal image sensor and a method of manufacturing the same are provided. A row electrode and a column electrode are formed on a substrate. A multi-layer stack includes a sensing layer, a first sensing electrode and a second sensing electrode which are in contact with the sensing layer with a channel formed between the first sensing electrode and the second sensing electrode, an absorbing electrode connected to the first sensing electrode, an insulating layer configured to insulate the absorbing electrode from the second sensing electrode and the sensing layer, and a protecting layer configured to cover an exterior. Supports are configured to allow the multi-layer stack to float with respect to the substrate. A first intervening electrode and a second intervening electrode are configured to connect the low electrode and the column electrode to the first sensing electrode and the second sensing electrode through the supports.

Abstract: Disclosed is an apparatus for processing a substrate, the apparatus including: a chamber providing a processing space; an electrode unit for generating first plasma in the processing space and having opposing electrodes; a coil unit located in an upper side of the processing space, and for generating second plasma supplied into the processing space; and a remote plasma unit for supplying radicals to the processing space.

Abstract: A semiconductor device includes first and second active patterns adjacent to each other in a first direction, each of the first and second active patterns including first and second edge portions spaced apart from each other, a word line crossing between the first and second edge portions of each of the first and second active patterns and extending in a wave shape in the first direction, a bit line on the first edge portion of the first active pattern, and a storage node contact on the second edge portion of the first active pattern, wherein the first active pattern extends in a second direction intersecting the first direction, and the second active pattern extends in a third direction that is symmetrical to the second direction with respect to the first direction.

Abstract: A semiconductor memory device is provided. The device includes a cell structure, a peripheral structure, and an interconnection structure sequentially stacked on a support substrate, in which the cell structure includes lower electrodes, a dielectric layer and an upper electrode with the dielectric layer and the upper electrode sequentially covering the lower electrodes, the peripheral structure includes a peripheral substrate and transistors disposed on a front surface of the peripheral substrate, and an upper surface of the upper electrode faces a back surface of the peripheral substrate.

Abstract: An image sensor includes; a substrate including a first surface and a second surface; a first pixel region; a second pixel region; a third pixel region; a first lens on the first pixel region; a second lens on the second pixel region and the third pixel region; an element separation film in the substrate and being interposed between the first pixel region and the second pixel region; a first color filter to transmit light focused by the second lens to the second pixel region and the third pixel region; a color filter grid forming a region in which the first color filter is provided. The color filter grid includes a metal layer; and a protective film on the color filter grid and in contact with the first lens and the second lens. The first lens is on the second surface.

Abstract: The present invention relates to a cryogenic chamber for impact testing, which comprises in one aspect a container having a sidewall formed by at least two layers and an upper side opened, wherein the sidewall includes a first sidewall and a second sidewall shaped to surround the first sidewall, the first sidewall partitions a first space in which a specimen may be arranged, the second space partitions a second space to perform thermal insulation treatment between the first sidewall and the second sidewall, the second space has a structure in which the upper side is closed, and a first cooling medium is continuously supplied to the second space, thereby blocking heat transfer between the first space and the outside, while a second cooling medium is continuously supplied to the first space, thereby cooling the specimen.

Abstract: An antenna alignment apparatus includes a first antenna alignment unit. The first antenna alignment unit may include: a flange coupled to a transmit antenna jig providing two-axis rotational motion; a first bearing coupled to the flange; a cylinder inserted into the first bearing to rotate; an optical fiber collimator inserted into and aligned with the cylinder and having a variable focal length; an optical fiber mounted on the optical fiber collimator; and a plurality of screws contacting an external side surface of the optical fiber collimator through an external side surface of the cylinder and aligning a central axis of the optical fiber collimator and a central axis of the cylinder.

Abstract: The present invention relates to an industrial boiler monitoring system for artificial intelligence-based exhaust gas analysis and fault diagnosis, which can construct a customized artificial intelligence-based learning model for diagnosing the concentration of exhaust gas to individual boilers of a customer and faults of various components, and diagnose the concentration of exhaust gas and faults of various components in real-time through the constructed learning model.

Abstract: An electronic apparatus is provided and includes a display module having a folding region foldable with respect to a folding axis and including a first non-folding region and a second non-folding region spaced apart from each other along a second direction, and a digitizer disposed under the display module, and the digitizer includes a base part including base layers, first and second sensing coils disposed between the base layers and insulated from each other, and an upper reinforcement part including a first reinforcement layer and a second reinforcement layer each of which is disposed on an upper surface of the base part, and which are spaced apart from each other along the second direction with the folding region therebetween, wherein at least a portion of the base part containing either synthetic rubber or polydimethylsiloxane (PDMS).

Abstract: A semiconductor device includes a substrate including a cell array region and a peripheral circuit region, capacitors on the cell array region of the substrate, peripheral transistors on the peripheral circuit region of the substrate, a first upper interlayer insulating layer on the capacitors and the peripheral transistors, a first upper contact electrically connected to at least one of the peripheral transistors, the first upper contact penetrating the first upper interlayer insulating layer, a first upper interconnection line provided on the first upper interlayer insulating layer and electrically connected to the first upper contact, a second upper interlayer insulating layer covering the first upper interconnection line, and a first blocking layer between the first upper interlayer insulating layer and the second upper interlayer insulating layer. The first blocking layer is absent between the first upper interconnection line and the first upper interlayer insulating layer.

Abstract: A package comprising a substrate, a first antenna device, and an integrated device. The substrate comprising a first surface and a second surface, where the substrate comprises a plurality of interconnects. The first antenna device is coupled to the first surface of the substrate, through a first plurality of solder interconnects. The integrated device is coupled to the second surface of the substrate. The package may include an encapsulation layer located over the second surface of the substrate, where the encapsulation layer encapsulates the integrated device. The package may include a shield formed over a surface of the encapsulation layer, where the shield includes an electromagnetic interference (EMI) shield.

Abstract: A film depositing composition including a Group 4 metal element-containing precursor compound and a method for forming a Group 4 metal element-containing film using same is described. The use of the film depositing composition including a Group 4 metal element-containing precursor compound achieves self-limiting film growth of ALD over a wide temperature range from low to high temperatures, enabling the formation of a Group 4 metal element-containing film for various purposes at various process temperatures. Particularly, according to the method for forming a Group 4 metal element-containing film of this invention, the growth per cycle (GPC) of ALD is consistent over a broad temperature range, thus making it possible to form a Group 4 metal element-containing film of uniform thickness even on surfaces with large aspect ratio trenches. Thus, the method can be advantageously utilized in manufacturing various semiconductor devices, such as DRAM, 3D NAND flash memory, and the like.

Abstract: A digitizer includes a first sensing coil disposed in an active region, a first dummy line disposed in the same layer as the first sensing coil, a second sensing coil disposed below the first sensing coil in the active region, a second dummy line disposed in the same layer as the second sensing coil, a bridge line disposed below the second sensing coil, and a third dummy line disposed in the same layer as the bridge line. At least two dummy lines among the first, second, and third dummy lines extend in the same direction.

Abstract: An active noise control method and system for a vehicle are provided. The active noise control method for a vehicle includes performing active noise control (ANC) to reduce noise introduced from the outside of the vehicle to the inside of the vehicle and received through a microphone, determining whether a level of residual noise of the noise reduced by the ANC is greater than a threshold value, and performing secondary path model re-measurement when an engine of the vehicle is turned off if the level of the residual noise is greater than the threshold value.

Abstract: A method of estimating active noise control performance of a vehicle includes performing ANC by reproducing an acoustic signal for reducing noise introduced from the outside to the inside of the vehicle through a speaker and receiving a residual signal remaining after noise reduction from a microphone, generating an estimation signal for a control signal for controlling output of the speaker such that the acoustic signal is reproduced during the ANC, generating an estimation signal for original noise before the ANC based on the residual signal and the estimation signal for the control signal, and estimating noise reduction performance based on the estimation signal for the original noise and the residual signal.

Abstract: A lane change control apparatus includes a processor configured to generate a second lane change path according to a head angle of a vehicle at a current position of the vehicle to try lane change again in response to a case where the lane change is canceled while the vehicle is performing the lane change according to a first lane change path and then the cancellation of the lane change is withdrawn while the vehicle is returning to an original lane of the vehicle; and a storage configured to store data and algorithms driven by the processor.

Abstract: Disclosed are an interfacing method and an apparatus for three-dimensional (3D) sketch. According to an example embodiment, the interfacing method for sketching in a virtual space of three dimensions includes determining a surface including an area in which a first user input is received in the virtual space to be a region of interest, controlling a position of the region of interest in the virtual space based on a second user input on the region of interest, and generating at least one sketch line belonging to the region of interest based on a third user input.

Abstract: A method of fabricating a semiconductor device. A cell area and a core area are defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.