Patents by Inventor Kwan-Sik Cho
Kwan-Sik Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220352216Abstract: An image sensor includes a substrate having first and second surfaces and first and second regions. Unit pixels including photoelectric conversion layers are arranged inside the first region. A pixel separation pattern extends from the first surface to the second surface in the first region, separates each of the unit pixels, and includes a pixel separation spacer film and a pixel separation filling film. A dummy pixel separation pattern extends from the first surface to the second surface in the second region, and includes a dummy pixel separation filling film. A wiring structure disposed on the second surface includes an inter-wiring insulating film and a first wiring. A first contact directly connects the dummy pixel separation filling film and connects the dummy pixel separation filling film to the first wiring. A height of the pixel separation filling film is greater than a height of the dummy pixel separation filling film.Type: ApplicationFiled: December 13, 2021Publication date: November 3, 2022Inventors: Min Ho JANG, Seung Kuk KANG, Hae Sung JUNG, Kwan Sik CHO, Ho-Chul JI
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Publication number: 20220149088Abstract: An image sensor includes a substrate, a photoelectric conversion region disposed inside the substrate, a first active region disposed inside the substrate to include a ground region, a floating diffusion region, and a channel region for connecting the ground region and the floating diffusion region, a substrate trench disposed inside the channel region, a transfer gate disposed on a face of the substrate to include a lower gate which fills a part of the substrate trench and has a first width, and an upper gate having a second width smaller than the first width on the lower gate, and a gate spacer disposed inside the substrate trench to be interposed between the ground region and the upper gate.Type: ApplicationFiled: July 23, 2021Publication date: May 12, 2022Inventors: Dong Mo IM, Ja Meyung KIM, Jong Eun PARK, Beom Suk LEE, Kwan Sik CHO
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Publication number: 20220139993Abstract: An image sensor includes a substrate having an element separation pattern, a first active region, and a ground region, the ground region being separated from the first active region by the element separation pattern, a transfer transistor including a transfer gate electrode on the first active region, the transfer gate electrode being separated from the ground region by the element separation pattern, a photo diode within the substrate, the photo diode being spaced apart from the transfer gate electrode, and a contact on the ground region, the contact being configured to receive a ground voltage.Type: ApplicationFiled: October 22, 2021Publication date: May 5, 2022Inventors: Dong Hyun KIM, Yong Sang PARK, Hae Yong PARK, Jong Eun PARK, Kwan Sik CHO
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Patent number: 10712497Abstract: Photonic integrated circuit packages having improved integration, and methods of manufacturing such photonic integrated circuit packages, are provided. As an example, a photonic integrated circuit package may include a substrate, a first insulating layer on the substrate, a photonic core layer on the first insulating layer, and a second insulating layer on the photonic core layer. A photonic coupling device may be in the photonic core layer, and may be, as examples, at least one of a grating coupler or a photodetector. A concave mirror may extend into at least the second insulating layer. In some embodiments, the concave mirror may extend through the second insulating layer and into the first insulating layer.Type: GrantFiled: November 7, 2018Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ho Chul Ji, Kwan Sik Cho, Keun Yeong Cho
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Publication number: 20190265408Abstract: Photonic integrated circuit packages having improved integration, and methods of manufacturing such photonic integrated circuit packages, are provided. As an example, a photonic integrated circuit package may include a substrate, a first insulating layer on the substrate, a photonic core layer on the first insulating layer, and a second insulating layer on the photonic core layer. A photonic coupling device may be in the photonic core layer, and may be, as examples, at least one of a grating coupler or a photodetector. A concave mirror may extend into at least the second insulating layer. In some embodiments, the concave mirror may extend through the second insulating layer and into the first insulating layer.Type: ApplicationFiled: November 7, 2018Publication date: August 29, 2019Inventors: Ho Chul Ji, Kwan Sik Cho, Keun Yeong Cho
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Patent number: 9897753Abstract: An optical device includes a substrate; a trench in a portion of the substrate; a clad layer arranged in the trench; a first structure arranged on the clad layer to have a first depth; and a second structure arranged on the clad layer to have a second depth different from the first depth.Type: GrantFiled: December 22, 2016Date of Patent: February 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Kwon Bok, Kyoung-Ho Ha, Dong-Jae Shin, Seong-Gu Kim, Kwan-Sik Cho, Beom-Suk Lee, Jung-Ho Cha, Hyun-Il Byun, Dong-Hyun Kim, Yong-Hwack Shin, Jung-Hye Kim
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Patent number: 9786600Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.Type: GrantFiled: December 15, 2015Date of Patent: October 10, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho
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Publication number: 20170184786Abstract: An optical device includes a substrate; a trench in a portion of the substrate; a clad layer arranged in the trench; a first structure arranged on the clad layer to have a first depth; and a second structure arranged on the clad layer to have a second depth different from the first depth.Type: ApplicationFiled: December 22, 2016Publication date: June 29, 2017Inventors: JIN-KWON BOK, KYOUNG-HO HA, DONG-JAE SHIN, SEONG-GU KIM, KWAN-SIK CHO, BEOM-SUK LEE, JUNG-HO CHA, HYUN-IL BYUN, DONG-HYUN KIM, YONG-HWACK SHIN, JUNG-HYE KIM
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Publication number: 20160104671Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.Type: ApplicationFiled: December 15, 2015Publication date: April 14, 2016Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho
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Patent number: 9231104Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.Type: GrantFiled: October 29, 2014Date of Patent: January 5, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho
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Publication number: 20150048444Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.Type: ApplicationFiled: October 29, 2014Publication date: February 19, 2015Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho
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Patent number: 8929693Abstract: A semiconductor package and a semiconductor device including the same. The semiconductor package includes: a package substrate; a plurality of connection elements that are disposed on the package substrate; and a semiconductor chip that includes at least one optical input/output element that transmits/receives an optical signal to/from the outside at an optical input/output angle with respect to a direction perpendicular to a bottom surface of the package substrate, and is electrically connected to the package substrate through the plurality of connection.Type: GrantFiled: March 7, 2013Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-jae Shin, Hyun-il Byun, Kwang-hyun Lee, Kwan-sik Cho, Ho-chul Ji, Jung-hyung Pyo, Kyoung-ho Ha
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Patent number: 8901645Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.Type: GrantFiled: April 17, 2013Date of Patent: December 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho
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Publication number: 20140212087Abstract: A method of manufacturing a semiconductor apparatus includes forming a gate structure and an etch stop layer structure on a substrate including first and second regions. The gate structure is formed in the first region, and the etch stop layer structure is formed in the second region. A first insulating interlayer is formed on the substrate to cover the gate structure and the etch stop layer structure. The first insulating interlayer is partially removed to expose the etch stop layer structure. The exposed etch stop layer is removed to expose the substrate. An optical device is formed on the exposed substrate.Type: ApplicationFiled: January 24, 2014Publication date: July 31, 2014Applicant: Samsung Electronics Co., LtdInventors: Kwan-Sik CHO, Jung-Hye KIM, Yong-Hwack SHIN
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Publication number: 20140139900Abstract: A wavelength tunable optical transmitter includes a first waveguide receiving incident light through an input port and outputting the incident light to a first output port, a resonant modulator adjacent to the first waveguide and whose resonant wavelength is variable, and a second waveguide disposed optically in parallel to the first waveguide and outputting emitted light to a second output port. The resonant modulator includes a silicon resonator constituted by a crystallized silicon film in the form of a closed loop between the first and second waveguides, a first electrode within the silicon resonator and constituted by a silicon film of a first conductivity type, and a second electrode extending alongside part of the outer circumferential surface of the silicon resonator and constituted by a silicon film of a second conductivity type.Type: ApplicationFiled: August 21, 2013Publication date: May 22, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Jae SHIN, Jin-Kwon BOK, Beom-Suk LEE, Kwan-Sik CHO, Ho-Chul JI, Sang-Hun CHOI, Kyoung-Ho HA
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Publication number: 20130330035Abstract: A semiconductor package and a semiconductor device including the same.Type: ApplicationFiled: March 7, 2013Publication date: December 12, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-Jae Shin, Hyun-il Byun, Kwang-hyun Lee, Kwan-sik Cho, Ho-chul Ji, Jung-hyung Pyo, Kyoung-ho Ha
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Patent number: 8557664Abstract: A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.Type: GrantFiled: October 3, 2012Date of Patent: October 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Kwan-sik Cho, Kwang-youl Chun, Jae-man Yoon, Bong-soo Kim
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Publication number: 20130228856Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.Type: ApplicationFiled: April 17, 2013Publication date: September 5, 2013Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho
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Patent number: 8461687Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.Type: GrantFiled: March 28, 2011Date of Patent: June 11, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho
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Patent number: 8293603Abstract: A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.Type: GrantFiled: January 18, 2011Date of Patent: October 23, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kwan-sik Cho, Kwang-youl Chun, Jae-man Yoon, Bong-soo Kim