Patents by Inventor Kwan Yee Martin Lee
Kwan Yee Martin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8856201Abstract: Multiplier circuitry that efficiently utilizes the hard and soft logic regions of a programmable logic device (PLD) is provided. The multiplier circuitry includes a partial product generation block, a compression block (e.g., a carry-save adder), and an carry-propagate adder stage. The partial product generation and compression block are implemented in hard logic while the carry-propagate adder is implemented in soft logic. Local or global routing may be used to connect the hard and soft multiplier components. The multiplier may further include a selectable input register in hard logic and/or a selectable output register in soft logic. This mixed-mode design allows for a substantial savings in the amount of hard logic required to implement the multiplier without a significant decrease in multiplier performance.Type: GrantFiled: April 16, 2012Date of Patent: October 7, 2014Assignee: Altera CorporationInventors: Martin Langhammer, Kwan Yee Martin Lee, Ali H. Burney
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Patent number: 8301681Abstract: A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for performing floating point operations. The floating point circuitry preferably includes rounding and normalization circuitry. To perform mantissa multiplications, the floating point circuitry preferably relies on the aforementioned multipliers of the specialized processing block.Type: GrantFiled: June 5, 2006Date of Patent: October 30, 2012Assignee: Altera CorporationInventors: Kwan Yee Martin Lee, Martin Langhammer, Triet M. Nguyen, Yi-Wen Lin
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Patent number: 8266198Abstract: A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a look-ahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.Type: GrantFiled: June 5, 2006Date of Patent: September 11, 2012Assignee: Altera CorporationInventors: Kwan Yee Martin Lee, Martin Langhammer, Yi-Wen Lin, Triet M. Nguyen
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Patent number: 8266199Abstract: A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.Type: GrantFiled: June 5, 2006Date of Patent: September 11, 2012Assignee: Altera CorporationInventors: Martin Langhammer, Kwan Yee Martin Lee, Orang Azgomi, Keone Streicher, Yi-Wen Lin
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Patent number: 8041759Abstract: A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations, including finite impulse response (FIR) filters and infinite impulse response (IIR) filters. By using the programmable connections, and in some cases the programmable resources of the programmable logic device, and by running portions of the specialized processing block at higher clock speeds than the remainder of the programmable logic device, more complex FIR and IIR filters can be implemented.Type: GrantFiled: June 5, 2006Date of Patent: October 18, 2011Assignee: Altera CorporationInventors: Martin Langhammer, Kwan Yee Martin Lee, Orang Azgomi, Keone Streicher, Robert L. Pelt
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Patent number: 7836117Abstract: A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.Type: GrantFiled: July 18, 2006Date of Patent: November 16, 2010Assignee: Altera CorporationInventors: Martin Langhammer, Kwan Yee Martin Lee, Triet M. Nguyen, Keone Streicher, Orang Azgomi
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Publication number: 20070185952Abstract: A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.Type: ApplicationFiled: June 5, 2006Publication date: August 9, 2007Applicant: Altera CorporationInventors: Martin Langhammer, Kwan Yee Martin Lee, Orang Azgomi, Keone Streicher, Yi-Wen Lin
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Publication number: 20070185951Abstract: A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a look-ahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.Type: ApplicationFiled: June 5, 2006Publication date: August 9, 2007Applicant: Altera CorporationInventors: Kwan Yee Martin Lee, Martin Langhammer, Yi-Wen Lin, Triet M. Nguyen