Abstract: An electronic system electronic device includes: an internal battery, an external battery, a memory and a plurality of function modules. The internal battery is configured to generate a first power signal. The external battery is configured to be separated from the electronic device, and to generate a second power signal. The memory is configured to operate based on the first power signal. The plurality of function modules are configured to operate based on the second power signal.

Abstract: An electronic system electronic device includes: an internal battery, an external battery, a memory and a plurality of function modules. The internal battery is configured to generate a first power signal. The external battery is configured to be separated from the electronic device, and to generate a second power signal. The memory is configured to operate based on the first power signal. The plurality of function modules are configured to operate based on the second power signal.

Abstract: A memory system includes a memory device including a plurality of memory dies and a controller coupled to the plurality of memory dies via plural data paths. The controller is configured to select a first path among the plural data paths, activate unselected paths among the plural data paths, and perform a calibration operation for data communication between the controller and a first memory die coupled to the controller via the first path among the plural memory dies while the unselected paths are activated.

Abstract: An electronic system electronic device includes: an internal battery, an external battery, a memory and a plurality of function modules. The internal battery is configured to generate a first power signal. The external battery is configured to be separated from the electronic device, and to generate a second power signal. The memory is configured to operate based on the first power signal. The plurality of function modules are configured to operate based on the second power signal.

Abstract: An electronic system electronic device includes: an internal battery, an external battery, a memory and a plurality of function modules. The internal battery is configured to generate a first power signal. The external battery is configured to be separated from the electronic device, and to generate a second power signal. The memory is configured to operate based on the first power signal. The plurality of function modules are configured to operate based on the second power signal.

Abstract: An electronic system electronic device includes: an internal battery, an external battery, a memory and a plurality of function modules. The internal battery is configured to generate a first power signal. The external battery is detachably attached to the electronic device, the external battery configured to generate a second power signal. The memory is configured to operate based on the first power signal. The plurality of function modules are configured to operate based on the second power signal.

Abstract: Provided are an application processor and a semiconductor system including the same. The semiconductor system includes the application processor, which may include a first register value and of which an operation is controlled by the first register value. The semiconductor system also includes a semiconductor device, which may include a second register value and of which an operation is controlled by the second register value, and a memory storing a third register value that is a copy of the first register value and a fourth register value that is a copy of the second register value. If the stored third register value is changed, the changed third register value is mapped onto the first register value of the processor, and if the fourth register value is changed, the changed fourth register value is mapped onto the second register value.

Abstract: An electronic system electronic device includes: an internal battery, an external battery, a memory and a plurality of function modules. The internal battery is configured to generate a first power signal. The external battery is detachably attached to the electronic device, the external battery configured to generate a second power signal. The memory is configured to operate based on the first power signal. The plurality of function modules are configured to operate based on the second power signal.

Abstract: A method is provided for operating a volatile memory device. The method includes performing a first initialization operation for the volatile memory device based on a boot code received from an external memory controller, storing the boot code in an internal register, reading the boot code stored in the internal register based on a first signal received from the external memory controller when the first initialization operation is not normally performed, and performing a second initialization operation for the volatile memory device based on the boot code read from the internal register.

Abstract: Provided are an application processor and a semiconductor system including the same. The semiconductor system includes the application processor, which may include a first register value and of which an operation is controlled by the first register value. The semiconductor system also includes a semiconductor device, which may include a second register value and of which an operation is controlled by the second register value, and a memory storing a third register value that is a copy of the first register value and a fourth register value that is a copy of the second register value. If the stored third register value is changed, the changed third register value is mapped onto the first register value of the processor, and if the fourth register value is changed, the changed fourth register value is mapped onto the second register value.

Abstract: A method is provided for operating a volatile memory device. The method includes performing a first initialization operation for the volatile memory device based on a boot code received from an external memory controller, storing the boot code in an internal register, reading the boot code stored in the internal register based on a first signal received from the external memory controller when the first initialization operation is not normally performed, and performing a second initialization operation for the volatile memory device based on the boot code read from the internal register.

Abstract: An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.

Abstract: An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.

Abstract: An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.

Abstract: A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence.

Abstract: A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.

Abstract: An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.

Abstract: A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.

Abstract: A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence.