Abstract: Configurations for a photonics assembly and the operation thereof are disclosed. The photonics assembly may include multiple photonics dies which may be arranged in an offset vertical stack. The photonics dies may emit light, and in some examples, an optical element may be a detector for monitoring properties such as the wavelength of the light. The photonics dies may be arranged in a stack as a package and the packages may be stacked or arranged side by side or both for space savings. The PIC may include combining and/or collimating optics to receive light from the photonics dies, a mirror to redirect the light, and an aperture structure. The aperture structure may include a region which is at least partially transparent such that light transmits through the transparent region of the aperture structure. The aperture structure may include an at least partially opaque region which may be used for directing and/or controlling the light launch position.

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

Abstract: Die reconstitution methods and dies with reconstituted contact bumps are described. In an embodiment, a die reconstitution method includes reconstituting a plurality of dies including first contact bumps of a first type, partially removing the first contact bumps, and forming second contact bumps of a second type on top of the partially removed first contact bumps, where the second type is different than the first type.

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

Abstract: Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die.

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip including a reconstituted chip-level back endo of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

Abstract: An inductive device is disclosed, including a first wire coupled to a first terminal and to a second terminal, a non-conductive material surrounding the first wire, and a magnetic film. The non-conductive material spans the region from the first terminal to the second terminal. The magnetic film surrounds at least a portion of the non-conductive material between the first terminal and the second terminal. The first wire has a first amount of inductance.

Abstract: An inductor can include a first substrate, a magnetic piece, and a conductor. The first substrate can be formed within a second substrate. The magnetic piece can be connected to a first side of the first substrate. The conductor can be formed within the second substrate, on the second substrate, or both. The conductor can have an input and an output. The conductor can be configured to surround the first substrate without being in contact with the first substrate and without being in contact with the magnetic piece.

Abstract: This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including package-on-packages (PoPs). The glass via bars can provide high density electrical interconnections in the PoPs. In some implementations, the glass via bars can include integrated passive components. Packaging methods employing glass via bars are also provided.

Abstract: An inductive device is disclosed, including a first wire coupled to a first terminal and to a second terminal, a non-conductive material surrounding the first wire, and a magnetic film. The non-conductive material spans the region from the first terminal to the second terminal. The magnetic film surrounds at least a portion of the non-conductive material between the first terminal and the second terminal. The first wire has a first amount of inductance.

Abstract: Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a “known good” substrate on a support substrate.

Abstract: Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a “known good” substrate on a support substrate.

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

Abstract: Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a first redistribution layer (RDL) and a second RDL, and a second level die is mounted on a top side of the first redistribution layer. In an embodiment, the first level die is an active die, less than 50 ?m thick.

Abstract: A finger biometric sensor assembly may include a finger biometric sensor integrated circuit (IC) die having a finger sensing area and a cover layer aligned with the finger sensing area. The finger biometric sensor may also include a direct bonding interface between the finger biometric sensor and the cover layer.

Abstract: Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a “known good” substrate on a support substrate.

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.