Abstract: There is disclosed a photodetector having two or more avalanche-gain layered structures and multi-terminals. The avalanche photodetector includes an emitter light absorption layer structure located between a collector layer and an emitter layer (top contact layer) stacked on a substrate. The photodetector further comprises multiple avalanche-gain layered structures consisting of a charge layer, a multiplication layer and a contact layer between the light absorption layer and said collector layer.

Abstract: There is disclosed a photodetector having two or more avalanche-gain layered structures and multi-terminals. The avalanche photodetector includes an emitter light absorption layer structure located between a collector layer and an emitter layer (top contact layer) stacked on a substrate. The photodetector further comprises multiple avalanche-gain layered structures consisting of a charge layer, a multiplication layer and a contact layer between the light absorption layer and said collector layer.

Abstract: The present invention relates to an electrical field absorbing semiconductor optical modulator, more particularly, to a high speed semiconductor optical modulator and a fabricating method thereof. The present invention includes a high speed semiconductor optical modulator, the optical modulator formed by stacking an n-type light-wave guiding layer, a light absorbing layer, a p-type light-wave guiding layer, a p-type clad layer, and a p-type ohmic contact layer on a substrate successively, the optical modulator having a ridge structure wherein the optical modulator is an electric-field absorbing type, and wherein width W3 of the light absorbing layer is less than the width W1 of the p-type ohmic contact layer. Accordingly, the present invention enables to provide high speed optical modulation of tens of giga rate of which modulating characteristics are excellent by reducing contact resistance and capacitance, which are the major problems of ruining the characteristics of an optical modulator, simultaneously.

Abstract: A method of forming a gate electrode of a compound semiconductor device includes forming a first insulating film pattern having a first aperture, forming a second insulating film pattern having a second aperture consisting of inverse V-type on the first insulating film pattern, forming a T-type gate electrode by depositing a conductivity film on the entire structure, removing a second insulating film pattern, forming a insulating spacer on a pole sidewall by etching a first insulating film pattern, and forming an ohmic electrode of the source and drain by self-aligning method using T-type gate electrode as a mask. Thereby T-type gate electrode of materials such as refractory metals can be prevented to be deteriorate because of high annealing, as well as it is stably formed, by using an insulating film. Ohmic metal and gate electrodes formed by self-aligning method can be prevented an interconnection by forming an insulating film spacer between these electrodes.

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract: The present invention relates to a bias stabilization circuit, specifically to a bias stabilization circuit for minimizing the current variations of amplification transistors caused by variations of device parameters which occur during the manufacturing of high-frequency integrated circuits using field-effect transistors, and caused by variations of supply voltage and temperature. In the present invention, the above problem is solved by configuring a level shifter circuit between the drain node and the gate node of the reference voltage generation transistor. Further, by using a constant current source utilizing a depletion transistor and series feedback resistors as a reference current, this circuit becomes stable against the variations of the device parameters as well as the variations of the temperature and supply voltage.

Abstract: The present invention relates to a gain control circuit for a low-noise amplifier. A gain control circuit of a 2-stage low-noise amplifier comprising an input stage noise matching circuit, an intermediate impedance matching circuit, a gain control circuit, and an output stage impedance matching circuit, said gain control circuit including: a feedback circuit connected to a transistor of second stage of the 2-stage low-noise amplifier, said feedback circuit detecting the amplified signal through the first stage and the second stage, and feeding the signal back through a switch circuit; and an attenuation circuit for compensating the harmonics of the input signal.

Abstract: The present invention relates to a gain controlled amplifier, and more particularly, to a gain controlled amplifier using active feedback and variable resistance. It is an object of the present invention to provide a gain controlled amplifier minimizing the gain and the degradation of power characteristics generated when adjusting gain in a variable gain amplifier which receives signals having different power levels, amplifies them in accordance with each power level and outputs output signals in a constant power level. In order to achieve the above object, a gain controlled amplifier in accordance with the present invention comprises an amplifier and an active feedback means for negative feedbacking the output of the amplifier to the input of the amplifier, and further has a feedback amount controller inputting the controlled feedback signal to the amplifier by controlling the feedback amount of said active feedback means.

Abstract: Disclosed is a method for manufacturing a vertical channel transistor comprising the steps of: selectively implanting a dopant of high concentration into a semiconductor substrate to form a source region; firstly etching the semiconductor substrate using an insulator and a first photoresist pattern as a mask; secondly etching the substrate using a second photoresist pattern having a shape corresponding to said source region as a mask; implanting a dopant of low concentration into the exposed substrate using said second photoresist pattern as a mask to form a vertical channel layer; implanting a dopant of high concentration into the exposed substrate using same mask to form a drain region; activating said dopants, and forming an ohmic contact layer on said drain region; thirdly etching using a third photoresist pattern for exposing the firstly etched portion of the substrate as a mask; depositing a gate metal on the substrate exposed by the thirdly etching; and wiring a metal, respectively.

Abstract: Disclosed is a micromirror for a hybrid optoelectronic integrated circuit, a method for manufacturing the same, a micromirror-photodetector assembly and an assembly of hybrid optoelectronic integrated circuit for receiving light. The micromirror the present invention comprises a silicon substrate and at least one V-shaped groove formed in the silicon substrate and the V-shaped groove has an inclined surface reflecting light emitted from an optical waveguide to a photodetector. The alignment of the photodetector and the optical fibers is achieved without an additional attachment equipment, by inserting the optical fibers into the V-groove.

Abstract: A method for fabricating a T-shaped gate electrode of a high speed semiconductor device such as HEMTs which is applied to high speed logic circuit including low-noise receivers and power amplifiers having a frequency of X-band or more respectively, and MMICs having a frequency of millimeter wave band. Such devices require a short gate length and a large sectional area of the gate pattern. The conventional photolithography techniques are in need of the resolution for fabricating a fine line width. Therefore, electron-beam lithography is most widely used. But, it is difficult to enhance throughput in manufacturing semiconductor devices because a lot of exposure time is required in the methods using electron beams. In the present invention, a silicon oxide film or a silicon nitride film is deposited on a mono-layered resist pattern. A dummy pattern corresponding to a leg of the gate is formed using the silicon oxide film or the silicon nitride film.

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract: The present invention relates to an equivalent circuit of a package ground terminal paddle which is used to mount a microwave integrated circuit, and more particularly, to an approximate equivalent circuit of the package ground terminal paddle by which the expressions of parasitic components can be easily expanded according to the number of gold wires that are down-bonded to the paddle, by introducing an equivalent circuit structure which takes the impedance component output from each terminal as one common impedance component and grounds the common impedance.

Abstract: There is disclosed a method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor having a good conformity and an improved speed characteristic, which includes the steps of sequentially laminating an underlying nitride film, an oxide film, a polycrystalline silicon film and an upper nitride on a semiconductor substrate on which devices are separated and a collector is formed; sequentially etching said upper nitride film and said polycrystalline silicon film using the emitter as a mask, and then forming a side wall nitride film; selectively wet-etching said oxide film to form a side base linker opening; burying said base linker opening with a polycrystalline silicon; oxidizing said polycrystalline silicon film buried into said base linker opening and then removing said oxide film by means of the selective wet-etch process; removing said upper nitride and then forming a silicon/silicon germanium film as a base film on the exposed thereof; and forming an emitter said silicon/silicon germ

Abstract: This invention provides infrared sensing photodetector and a method therefor which provides a structure for effectively absorbing a light incident in a normal direction on a substrate, and a method compatible with existing processes for making integrated circuitry.

Abstract: The invention relates to a method of fabricating a compound semiconductor device by forming a first and a second compound semiconductor devices having a plurality of different epitaxial layers on a common semiconductor substrate.

Abstract: A fabrication method of a semiconductor device is disclosed. A T-shaped gate used for decreasing the gate resistance is adopted in fabricating an ultrahigh frequency and low-noise device. According to the present invention, a gate pattern is formed by a dual exposure technique, a thin metal film is formed, a pattern for plating is formed, and a gate is formed by electroplating, whereby decreasing a gate length and gate resistance. Therefore, the cost of production is decreased, the yield is improved, and the noise figure is minimized.

Abstract: A method for correcting a high frequency measurement error which can exactly correct the high frequency measurement error even with the use of a standard devices of which characteristic have not been verified by calculating the characteristic impedance of the correction device from the characteristics of an auxiliary measuring device calculated by using a general error correction method, and calculating again the once calculated characteristics of the auxiliary measuring device.

Abstract: A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing layer on the insulating layer to planarize the surface of the semiconductor substrate; etching the planarizing layer to expose the top of the insulating layer; isotropically etching the insulating layer to expose the gate pattern using the planarizing layer as a mask; etching the exposed gate pattern to selectively expose the semiconductor substrate; depositing a gate metal to cover the exposed substrate, the insulating layer and the planarizing layer, to form a T-shaped gate; and simultaneously removing the planarizing layer, thereby forming a T-shaped gate metal with improved productivity.

Abstract: An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the