Abstract: A computer system which includes a central processing unit including a first processing unit that performs basic processing functions and a co-processing unit that performs multiple specialized processing functions concurrently with the first processing unit, an arrangement for detecting the occurrence of a function causing an exception in a result produced by the coprocessing unit, an arrangement for specifying to the first processing unit any exception in a result produced by the coprocessing unit, an arrangement for using the first processing unit to implement any function which causes an exception in a result produced by the co-processing unit, an arrangement for storing the identification of the instruction being handled by the first processing unit when a function causing any exception in a result produced by the co-processing unit occurs, and an arrangement for determing the instruction which produced the exception.

Abstract: The disclosure provides a storage protection (SP) array in each of two system controllers (SCs) in a multiprocessing system which has a shared main storage containing a plurality of basic storage modules (BSMs). The BSMs may be operated with block and page interleaved addresses. Each block in main storage is assigned a key-in-storage having an entry in one of the two arrays.A cross-interrogate (XI) bus connects between the SCs. Using the XI bus, each processor request is sent to an SP address register in every SP array.Each array is divided into a plurality of equal groups. Each group has a range identifier register and a comparator. The range identifier register is loaded with a value which controls the range of main storage addresses to which the group is assigned. All of the comparators in each array are connected to a high-order part of the SP address register for the array.

Abstract: A storage configuration table (BCA) has a plurality of register entries which are loaded with signals that assign absolute addresses to the physical locations in a computer system's main storage, which may have plural basic storage modules (BSMs). Each BCA entry contains plural fields which relate a range of absolute addresses to a BSM section, including (1) a port select field which assigns a BSM port, (2) a BSM select field which assigns one of plural BSMs connected to the port, (3) a BSM section modified field to change the BSM section assigned to the range of absolute addresses, and (4) a restricted system area (SA) range select field that can assign a SA to a respective BSM section, and specify the SA size. Each processor may restrict SA accesses to microprogram controlled storage operations under control of an authorization field in a storage request. The SA can flexibly be located in any one or more BSMs.

Abstract: In a multi-processor system which utilizes store-in-cache techniques, a queueing mechanism for insuring that all units that wish to interrogate a memory line will be permitted to interrogate the line. Backing store access requests for data that is contained in the cache of another processor are queued until they can be serviced. The access requests that pertain to particular data are issued from the queue on a first-in-first-out basis. No group of interrogating units will be able to lock out another unit that wishes to interrogate.